Cyclone III configuration

[Altera_Forum]

I'm about to spin my Cyclone 3 board and want to be sure I get the configuration stuff wired correctly. 

 I'm using a JTAG connection to the USB Blaster and a Serial Config Device (active serial) WITHOUT the USB Blaster Header (I'm writing the serial config device through the FPGA using the serial flash loader ).  According to page 10-73 of the Cyclone III Device Handbook I need to connect the JTAG pull-ups to VCCA which is 2.5 Volts.   Note (1) says that the pullups for nSTATUS and CONF_DONE should also be connected to the "same supply voltage as the USB-Blaster" which (according to note (6)) must be 2.5V.  It also says on page 10-28 that nSTATUS, nCONFIG and CONF_DONE must be connected to the VCCIO supply of the bank in which the pin resides.  nSTATUS and nCONFIG are in Bank 1. CONF_DONE is in bank 6.  Putting this all together implies that both bank 6 band bank1 MUST HAVE VCCIO of 2.5V!! WHICH I DON"T USE AT ALL ANYWHERE!!!!!  Is this device really this horribly designed ? or is the data sheet misleading ? (to use the more polite term)  Does anyone know what the real story is???  Thanks Rob

[Altera_Forum]

Funny post :) 

 The real story is that you CAN connect the JTAG pins via pull-up to 3.3V, but it is not recommended because the overshoot caused by the download cable may damage your FPGA. So if you are going to be really careful, go ahead and use 3.3V for JTAG.  If you decide to use the recommended 2.5V for JTAG though, you can still use 3.3V or whatever else VCCIO you need for any bank, including 1 and 6. Voltage level translators (especially the step-down ones) are really simple, use a resistor divider to get your 2.5V level CONF_DONE and whatnot :)  Read the ciii design guidelines (http://www.altera.com/literature/an/an466.pdf), page 22 onwards, for info about JTAG connections.  Edit: by the way, where did you get page 10-73 on the Cyclone III Handbook, my copy I downloaded just now stops at page 10-70 before jumping to 11-

[Altera_Forum]

Not using bank 1 & 6 at all is actually great news for your purposes! 

 Remember, just because you do not use a particular bank does not excuse you from powering each bank with some voltage!  In your case, just go ahead and connect the Vccio for those banks to 2.5 volts (as well as any other bank you are not planning to use.  Hope this helps.

[Altera_Forum]

No, it's the 2.5V I don't use anywhere - as a signalling level. I do use it for the VCCA and VCCD_PLLn pins. I need every pin I can get and will definitely use the IO banks 1 and 6.  

_________   I had the older version of the databook which had a mistake which was corrected in the newer version.  The old version had us connecting the pull-up of the nSTATUS and CONF_DONE to the "same supply voltage as the USB-Blaster" the new version corrects this to "the VCCIO supply of the bank in which the pin resides".  This still leaves me with a 2.5V signalling environment on bank 1. As I said before I don't have any 2.5V signals on my board.   (To Clancy: What do you mean by "be really careful" with the USB Blaster? It seems to me that either it blows up the FPGA's inputs or it doesn't, I don't see how I can be "really careful".)  Is there some way to add protection diodes to the JTAG signals and then use 3.3V for both the JTAG and Bank 1? ... or perhaps a buffer would be safer?

[Altera_Forum]

Recently I received prototype boards in which I attached the pull-ups for the TDI and TMS pins to 2.5V like page 10-73 note 6 says is appropriate for my ByteBlaster II. After having problems with the JTAG I started to do more research to find out that the JTAG pins reside in bank1 of the Cyclone III EP3C25F256 which I have tied to 3.3V. To appease the panic setting in, I wanted see in print that the JTAG port could be used at 3.3V with a CIII part. (The fix to make this port 2.5V would require disconnecting BGA pins from the power plane--much easier to connect my pull-ups to 3.3V) I found the following document on the Altera site which says 3.3V is acceptable. Unfortunately as far as I can tell this was missing from the configuration chapter (CH10) in the manual.  

  Chapter 14, Page 14-14  IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone III Devices  http://www.altera.com/literature/hb/cyc3/cyc3_ciii51014.pdf

[Altera_Forum]

Hello, 

 when you read the Cyclone III handbook's configuration chapter, you could wonder, if the device is 3.3V tolerant at all, but from the maximum ratings, this is the case without doubt, including JTAG and configuration interface. Comparing Cyclone II and III maximum ratings, the margin for voltage overshoot versus time is clearly smaller, but the absolute maximum ratings are nearly unchanged. Thus a configuration circuit that could damage Cyclone III devices would also be harmful to Cyclone II and others, usually operating with 3.3V powered configuration, provided the datasheet values are comparable.  But a protection circuit for an external connected configuration interface is menaningful anyway, e. g. a 100 ohms series resistor with a dual schottky diode connected to GND/VCCIO. It should be able to guarantee the allowed AC and DC ratings for I/O oins, except with ESD pulses.  To my opinion, the new thing with Cyclone III configuration interface is the VCCA dependency and the issues arising when VCCIO is powered after VCCA or rising non-monotonically. I guess, Altera developers have been somewhat suprized, how much confusion at customers side could be caused by some simple design changes. Afterwards, they took the easy way and ordered that Cyclone III configuation should be powered by 2.5V VCCIO connected to VCCA, exclusively. This, by the way, would also reduce the danger of overshoot induced damages.  I think, this could actually be a good advice for completely new designs. But customer may have different motives to continue with mainly 3.3V VCCIO, e.g. continuation of existing designs or device stock. Altera application engineers should rather help the customer to realize their design requirements as far as possible than suggesting arbitrary changes.  Regards,  Frank

[Altera_Forum]

this question is there is a cs pin of ADI level shifter ,it used the voltage of USB cable.so you must use the usb cable connect to PC.

[Altera_Forum]

Hello, 

 I not sure, if I understand the question exactly. But the USB Blaster versions I know don't drive out voltage that isn't derived from target VCC (pin 4). Would be very surprized if this had been changed.  Regards,  Frank

[Altera_Forum]

This is what they say about interfacing a CIII device for AS or PS configuration. And it's confusing reading this thread which kinda suggest to use 2.5 V :rolleyes:  

 http://www.altera.com/support/kdb/solutions/rd10152007_741.html  Solution ID: rd10152007_741 Last Modified: Oct 30, 2007 Product Category: Devices Product Area: Configuration Product Sub-area: Active Serial (AS)  problem How do I interface a Cyclone® III device with its configuration device in Active Serial or Active Parallel configuration scheme?  solution in an active serial (as) configuration scheme for cyclone iii device, the vccio of i/o bank 1 must be 3.3v. In an Active Parallel (AP) configuration scheme for Cyclone III device, the VCCIO of banks 1, 6, 7 and 8 must be the same and must be either 1.8, 2.5, 3.0 or 3.3V. altera® recommends that you do not use level shifters between a configuration device and the cyclone iii device in any active (as or ap) configuration scheme.  Can someone please clarify this. I wanna use the scheme in figure 10-29 :eek:

[Altera_Forum]

Hello, 

 using 2.5V for JTAG interface is an Altera suggestion from Cyclone III manual respectively AN466 cyclone iii design guidelines. It hasn't been invented in this thread. There are understandable reasons for this suggestion, but is also obvious that it doesn't fit all applications. Basically, configuration interface (including JTAG) can use VCCIO up to 3.3V as with previous devices if some precautions are observed.  With AS configuration, 3.3V VCCIO in the respective bank should be used, cause EPCS devices use 3.3V supply, the same with 3.3V standard flash in AP Mode. That's what the quoted knowledge base entry says.  With AS and CIII, you have two options: The traditional combined circuit, requiring separate configuration connectors for AS and JTAG, the AS part as shown in figure 10-28 or the new "smart" CIII variant, programming AS device through a SFL JTAG instance, as in figure 10-29. (I assume, that JTAG interface should be always present for development and test support) You may ask, why the two figures don't clearly set AS VCCIO to 3.3V as requested by the knowledge base? I don't know.  Regards,  Frank

[Altera_Forum]

Hi Frank 

Thanks for the reply, couple more clarifications if possible. Again this is for AS as in figure10-29   1) because I'm using an EPCS device nSTATUS and nCONFIG should be pulled-up to 3.3V and the VCCIO for the bank where these pins reside should also be 3.3V?  2) CONF_DONE should be pulled up to VCCIO of the bank where the pin reside, in my case (2.5V)?  3) VCCA shown on figure 10-29 for the JTAG pull ups is 2.5V?  Thanks

[Altera_Forum]

Hello, 

 yes, to follow Altera recommendations, you should do so. Regarding the different pull-up voltages, I think that you could supply all pull-ups from 2.5 V as well, cause this also complies with general MultiVolt rules.   In most cases, AS would be functional with B1 supply of 2.5V. However, according to the official rules, VCCIO of 2.5V isn't suited as output to 3.3V logic - because of a too low margin to LVCMOS minimum high level of 0.7 * 3.3 = 2.31V.  Regards,  Frank

[Altera_Forum]

Thanks frank

[Altera_Forum]

I'm about Cyclone III ep3c5e144.  

JTAG lines behave strangely. I connected the JTAG pull-ups to VCCA which is 2.5 Volts. But they are equal to 0. MSEL = 101 (to VCCA). When I connect to ByteBlaster-MV (VCCA 2.5 V) I see signals at the inputs (TDI, TMC, TCK), but TDO is always 0!! So programmer can't see board ("Can't acces JTAG chain").  Everything was good with Cyclone, CII. What I do not understand? What did I miss?  Thanks.

[Altera_Forum]

Hi Vit 

with the 144 pin package you should take the following into consideration " the e144 package has an exposed pad at the bottom of the package. this exposed pad is a ground pad that must be connected to the ground plane on your pcb. this exposed pad is used for electrical connectivity, and not for thermal purposes."  Hope this helps

[Altera_Forum]

I don't doubt, that the exposed pad should be connected, but I wouldn't expect that omitting this connection would cause failure of configuration. But I may be wrong. Did you try?

[Altera_Forum]

Hi, lynx. 

Thanks a lot. You are absolutely right. Now I see signals, that I have to see. I wasn't attentive.

[Altera_Forum]

--- Quote Start ---  I don't doubt, that the exposed pad should be connected, but I wouldn't expect that omitting this connection would cause failure of configuration. But I may be wrong. Did you try?  --- Quote End ---    As lynx said, the e144 package has an exposed pad at the bottom of the package. this exposed pad is a ground pad that must be connected to the ground plane on your pcb. (EP3C5, Pin-Outs, Note 6).  there is not connection between this pad and gnd. if this pad is not connected, c iii doesn't work correct

[Altera_Forum]

I've spoken to a rep, and he told me something that I think relates to all of this. he said the altera-made usb blaster is a piece of **** and has a bad signal that gives many people problems, and to always use terasic's cable instead. 

 This pretty much mirrors post# 2, "The real story is that you CAN connect the JTAG pins via pull-up to 3.3V, but it is not recommended because the overshoot caused by the download cable may damage your FPGA. So if you are going to be really careful, go ahead and use 3.3V for JTAG."  But in response to that post, a few other people asked, "wth does 'be careful' mean?" It seems the answer is to buy Terasic's cable. I would also use 3.3V, since that IS what the IO banks are running at and are expecting to see, and 2.5V is just a work-around.

[Altera_Forum]

Such inofficial statements may be understandable by the amount of service requests and customer complains related to JTAG configuration. I can't see, that the Terrasic variant is generally superior to Altera, I could also report an example where only Altera is working correctly and a customer, who uses a ESD protection circuit for JTAG interface in all designs never had any JTAG problems, with either Altera or Terrasic Blaster . 

 Apart from the special problem of getting overshoots that may damage the FPGA, which can be effectively eliminated by protection circuits, most JTAG problems are centered around TCK signal quality while setup and hold times and levels of the other signals are far from being critical normally. So any means, that achieves a clear, monotic signal at the FPGA TCK pin is a solution for the issue to my opinion.

[Altera_Forum]

FvM, it is very difficult to understand you. You should break up your sentences into smaller ones. (I learned recently that German has special features to build up very complex sentences. However, in English doing that is usually a very bad idea, especially if you're not a good speaker.) 

 "I can't see, that the Terrasic variant is generally superior to Altera, I could also report an example where only Altera is working correctly and a customer, who uses a ESD protection circuit for JTAG interface in all designs never had any JTAG problems, with either Altera or Terrasic Blaster."  Do you mean to say that one customer had problems with the Terrasic cable, while a second customer never had any problems with either one? Do you know what voltages the two customers were using?  However, you do seem to agree that the Terrasic cable doesn't have the overshoot problems that the Altera cable has?  Also, wouldn't using 2.5V levels on a 3.3V IO bank be a cause for TCK problems? Any dips or ringing would be much more likely to cross the threshold voltage and cause double-clocking or a poor duty cycle.