Cyclone III queries.

[Altera_Forum]

Hi all, 

I just have a few queries regarding Cyclone III that I was hoping you guys could help me with. At the moment I am working on choosing an suitable FPGA for a new project. It´s the first time I have been landed with this responsibility and am a bit nervous about making a mess of it, so please forgive me if my queries seem a little basic!   1. Firstly in the Cyclone III datasheet it gives a list of what I/O standards are supported on each bank. Each bank is for example capable of supporting 3.3V LVTTL and LVDS depending on VccIo, but I understand these standards cannot be mixed within the one bank. i.e. I can only use LVDS or 3.3V LVTTL on any one bank. is this correct? I ask because on a previous project on a stratix 2 GX we had LVDS on bank 2 and also a 3.3V LVTTL input on the same bank with no issues. Is it ok to use different supported I/O standards for inputs but only one standard for outputs?     2. The device I am interested in is the EP3C16 in the F484 package. This device has 347 user I/O´s but my question is, if I use lets say 20 LVDS I/O´s, does this count as 20 or 40 I/O´s? I am assuming the extra 20 I/O´s were not included in the original 347 but it would be great if someone could just confirm this. The same would apply for any form of differential signals? Is it possible to use a differential I/O pin as a general purpose I/O in which case more user I/O´s could be obtained?   3. Finally, I was reading the Cyclone III datasheet and all 3 speed grades (6, 7, 8) are available as C-Grade, but only -7 for I-Grade. When I search on the Altera site (on the buy devices link) I only see the C grade devices despite the fact that the datasheet says it is offered. Does anyone know why this would be?  Also just out or curiosity why is only one speed grade offered in industrial grade? Is this to do with lower demand for I-Grade material in smaller FPGA´s?     Many thanks for any guidance on the above queries.

[Altera_Forum]

1. Very simply, you can mix I/O standards in a bank, but you can't mix I/O supply voltages. LVDS must be supplied with VCCIO of 2.5V. You also can place 3.3V inputs in this bank, but no 3.3V outputs (cause Voh doesn't meet the specification). The device handbook tells in detail how and why. 

 2. 347 user I/O mean pins. A LVDS in- or output need two (adjacent) pins. It's generally advisable to perform pin assignment in the Pin Planner tool, to be aware of any incompatibilties in time.  3. Due to temperature dependant timing parameters, the fastest speed grade most likely isn't available in industrial grade. I think, you're right regarding limited demand and slowest grade.

[Altera_Forum]

1) As I understand it you can use LVTTL and LVDS in the same bank, they just need to use the same voltage.  

2) 20 LVDS pairs would use 40 I/O pins.

[Altera_Forum]

Rather than trust my understanding of what the device handbook says about some things, I prefer to create test cases in Quartus to see for sure how it works. 

 You can have a 3.3-V LVTTL input in an I/O bank containing LVDS. LVDS uses a 2.5V VCCIO, and that VCCIO is acceptable for 3.3V inputs. In Cyclone III you will probably get a warning with the help page for the warning referring you to Application Note 447.  The I/O count will use 2 of the available I/Os for each of the differential pairs. A single LVDS signal is a differential pair using 2 I/Os. If you think you might use almost all the available I/Os, be careful about something else affecting how these are counted. I forget how special pins are included in the stated quantities of available and used I/Os. I had a situation in some device where I had to look at this very closely in Quartus to see for sure how many I/Os were actually available for regular signals.  Before you commit to a pin-out for board layout, have a Quartus project that contains at least your I/Os, PLLs, and configuration scheme. Use dummy logic as necessary to keep the clocks from synthesizing away. If you are using IP with special I/O restrictions like a DDR memory interface, then include that IP in the project used to do the pin-out check. When using a combination of I/O standards where certain pins must be kept a certain distance from other pins, include enough dummy logic to make the data pins toggle or use "Toggle Rate" assignments. Run at least I/O Assignment Analysis, preferably the complete Fitter.

[Altera_Forum]

Many thanks for the replies. Things are clearer now. 

 Brad: Could you please explain to me the importance of using a Quartus project that contains at least your I/Os, PLLs, and configuration scheme and dummy logic. Before reading your post I thought just defining the I/O and checking that I had sufficient pins available would be enough at this stage. But I´m interested to know how it should be done properly and would be grateful if you could let me know of the benifits of following that approach     Also just another query or two:   I am currently doing putting together a Quartus project to see which package would suit best. In the Pin Planner I am assigning each I/O(~220) to a specific pin. I remember some time ago someone telling me that there is a way of specifiying the bank and letting Quartus do the rest of the work i.e. picking a pin. I have tried to do this by assigning a bank under "location" in the pin planner but how do I get Quartus to elect a pin within that bank? or do I have to assign them on a one by one basis?   Also I have a mixture of LVDS and 3.3V LVTTL I/O´s in the design. In the pin planner I see a range of pins Q, S and P, N. From reading Quartus help, I understand that the DQ and DQS pins (Q, S) are suited to interfacing with memory, but can also be used as general I/O e.g. LVTTL. But could they also be used as LVDS or must i only use the DIFF_p or DIFF_n pins (p, n)?  I suppose essentially what I am asking is what is the difference in DQ, DQS and DIFF_n and DIFF_p (Q,S and DIFF_p, DIFF_n)? When I click show "differntial pin pair connections" in the pin planner it also pairs certain Q pins (DQ) with other Q pins, so for this reason I was thinking that they can also be used as LVDS but I just find it a little confusing to distinguish the difference.    Also, all of the differential pins (p, n) have the symbol saying they are only outputs. Why would this be. Where would I connect an input to?   When Altera say for example a certain FPGA has 347 I/O pins as in this case. Where can I find a break down of this i.e. how many differential I/O´s. I have been unable to find anything. Perhaps all the information I require is contained in the pin planner if I can understand it better.   Many thanks for the help

[Altera_Forum]

Brad is right, that you have to connect the pins to some logic for a final verification of a pinout. To allow parallelisation of work, it's usually O.K. to use the Pin Planner result to start schematic entry and possibly layout, but at least connect the said dummy logic before producing a prototype. It's better of course, if you are already able to verify the timing with a full design. You surely can imagine, that it's a matter of experience to foresee typical trapdoors in pin assignment. 

 If you have LVDS and LVTTL I/O, you need 2.5V and 3.3V banks, very simple. As said, you can place LVTTL inputs in a 2.5V bank but no outputs that require full Voh level.  I also agree with Brad, that some of your question can be answered more easily by trial, although Pin Planner is a powerful tool. Some details are possibly clearer in the device pinout files. Generally DQ/DQS and DIFFIO have no particular relation, they are simple optional pin functions, sometimes alternative at the same pin. With Cyclone families, all DIFFIO pairs can be used as input, output properties are different in different banks, e.g. some needing resistor networks.  The amount of DIFFIO pairs for different devices and packages is listed in the device handbook, also all other resources that are important in part identification. As an advantage, the Pin Planner also considers distance rules, that have to be kept with differential and voltage referenced I/O standards and may reduce the number of available pins in a design.