Cyclone III reset and configuration

[Altera_Forum]

Hi all. 

I currently develop a board with a Cyclone III (EP3C25) device. I want to have opinions on my configuration / reset circuit diagram (see attached file). The choices that i have made are :  - use of active serial configuration scheme with EPCS16 device  - use of JTAG for debug (SOF) and programming (JIC via SFL) as i have not enougth space on board to place the two connectors  - use of MAX823 supervisor to :  . restart configuration on power-up or when power fails or if watchdog occurs (ie if the blinking led is halted)  . create additonnal 140ms reset time after end of configuration to reset the internal FPGA logic previously configured  - creates "basic" VCCA with serie's diode and 10µF decoupling capacitors  - takes attention on active serial and JTAG ports to avoid dangerous overshoots :  . 47u serie's resistance on DATA0 of EPCS device (value to be confirmed)  . 47u / 100pF line adaptation to avoid EPCS DCLK transmission line reflexion (seen only on that signal on real board with equal lenth epcs non adapted lines)  . JTAG io level powered by VCCA (2.5V) to reduce JTAG levels produce by usb blaster (ie limit overshoot risks)  . MSEL pin configuration directly to gnd or vcca  . serie's resistance on TDO signal and additionnal pull-up as seen on some evaluation board schematics  . line adaptation on 4 JTAG signals as connected to non adapted usb blaster cable (as additionnal precaution to 2.5v powered jtag)   My interrogations are :  - first are my precautions sufficient to prevent FPGA damages ? (these FPGA seems to be quite "sensible")  - as i have never use SFL, is it a signicative time performance degradation when flashing epcs via JTAG ?  - i plan to populate my 470pF capacitor between the max823 supervisor and nConfig pin only when i have finish to debug as i think have a risk that my watchdog restart the configuration when i use JTAG loader : in others words what is the priority between SFL and EPCS config circuitry ?  - has anyone notes line reflexions on DCLK line ONLY (ie not on nCS and ASDI epcs lines ???)     Thanks. Best Regards.

[Altera_Forum]

Here are some answers to your extensive questions. 

Please note these are only my two cents. I don't assure you this is the optimum: I simply state what I usually do and this has never created problems with CIII devices so far.  - JIC via SFL : this is a common practice. Nobody wants an extra connector. Time performance is not an issue because you need to flash the device once when the board is deployed. - precautions against fpga damage : generally you only need to secure the i/o lines connected to outer world. Jtag is supposed to be used in a controlled environment and/or by competent personnel, so this is not critical. Anyway, for jtag lines I'd rather use 100ohm series resistor instead of the 47ohm+100pF to ground. - 470pF capacitor or, worse, open circuit, would prevent proper device reset in case MAX823 nRESET output is initially or permanently asserted. I think you can simply disable the MAX823 reset feature by simply leaving WDI unconnected. Then, directly connect reset to nCONFIG and place a removable jumper on WDI - I've never had problems with DCLK signal integrity. Usually EPCS is very near to FPGA, so this is not an issue. I always connected DCLK directly and never used a termination like yours.

[Altera_Forum]

Thanks for this fast response and experience about these subjects. 

 Good news for SFL .... so i keep the solution.  For JTAG line security i put these 47 ohms / 100pF to limit overshoot and (small) esd discharge without affect timing : in the same way, on epcs device i've put such a network on dclk because i don't want to place serie's resistance which could reduce timing margin on this link (i have already place epcs dataout serie's resistance as mentionned in datasheet so ...) : additionnaly i have noticed on a previous designed board (without any terminaison on epcs) that ringing are present ONLY on dclk line althought epcs device was very close to fpga and such a network works very well. My interrogation was about the fact that i have'nt notice ringing on datain and chip_select pin on epcs device ??? (ie output drivers strength on fpga are differents ???).  I dont understand your remarks for reset circuitry : i have already prototyped this solution on another board whish has only as connector (no jtag). It seems to work fine, ie device auto configure itself at power on and internal logic has an additionnal reset time made by max823 (as conf_done low maintains manual reset on max823) : additionnaly internal logic (processor and/or state machines) makes the led blinking to maintains an activity on wdi input : if internal logic has a failure (solar particles :-)) than wdi remains high or low and max823 makes a reset : i have add the capacitor in order to not only reset the design but reconfigure AND reset as failure could be in logic itself ... : my interrogation was mostly wath's happen when i will use the jtag sfl or sof programming feature ? Precisly if i use the default factory SFL then it will not included blinking and the max823 will assert reset low so a low pulse on nConfig will be generated : i think i will be a problem as if reconf is launched the SFL will be destroyed and then then jtag will not be able to flash anythink in epcs !!! my approach was to unconnect the 470pF to avoid this situation ... but as i am not sure about jtag / epcs priority ...  Thanks again.  Regards.