I have two Cyc III devices (master-slave, AS and PS respectively) + EPCS16 flash.
In both devices I have ROMs (megafunction), one in the master and two of them in the slave. All ROMs are initialized with .mif files.
The problem is: the slave ROMs are always broken, i.e. have bit errors, which can be seen in the In-system memory content editor (and also have bad CRC, which is calculated by the external CPU).
I can re-write content of ROM with ISMCE, and there are no errors then.
If slave is loaded from EPCS - there are errors.
If I try to reload slave via JTAG - there are errors.
I get no errors from quartus, not when programming EPCS, nor while JTAG operations. ROM megafunction themselves works correctly, i.e. I can read content of ROMs with external CPU with no problems, but content itself is broken.
Master is always working correctly - no errors, CRC is ok etc.
Connection is as shown in handbook, I also have 2 buffers on the DCLK and DATA[0] lines (74LVC1G125), but no series resistors (they are optional for 3.3V, according to handbook). Trace length from buffer to slave is about 110..120 mm.
Appreciate for any help.
I think I've found the problem.
There is a trace connected to pin 76 on the master and pin 99 on the slave. Trace is pulled up to 3.3V via 2.2k
This **bleep** resistor was dead, and the trace was actually floating.
I didn't use this pins before, so I can't reveal the resistor is dead.
As I start to use it, all logic became a total mess. Something worked, something not. By elimination I found the culprit.
I can't explain how this trace connected with loading errors (when FPGA not even in user mode), but the fact is - replacing resistor solved all problems, ROMs working now (though I don't use them anymore).
Thanks to all, problem solved!
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@FvM wrote:
is the erroneous ROM content reproducible or arbitrarily varying? In the former case, I suspect a bug of the programming file conversion tool.
It's arbitrarily varying. Sometimes it's only one bit failed, sometimes it's 5-6. Sometimes bits are the same, but most of time they are varying.
The file conversion tool is ok, because, as I said, I can update ROM content through the In-system memory content editor (ISMCE) with the same file used in .sof/.pof, and then the content is ok.
@FvM wrote:
"If I try to reload slave via JTAG - there are errors." What does this exactly mean? You didn't show the JTAG configuration, are the devices configured in a chain? <> I presume you have separate .sof files for both devices?
It means that if I use JTAG to reload .sof file for slave, the ROMs content is still broken. And again, it's different bits are failing.
Yes, ofc, they are in JTAG chain. I have 2 different .sof files, and I can reload one or both devices.
So, here is an example what I'm doing:
1. Power up the board, both devices loads themselfs from EPCS (AS/PS). Master ROM is ok. Slave ROMs are failed.
2. Reloading slave via JTAG - still have ROM errors.
3. Reloading ROMs via ISMCE - ROMs are ok.
@FvM wrote:
How should the master/slave AS configuration affect JTAG operation?
Idk. I assume some ringing somewhere on the board, both DCLK/DATA0 and TCK/TDI/TDO.
But why the slave loads at all? If there is some error check, it should fail, isn't it? Or there is no error check?
There is the ROM1 content in the slave after power up:
Then I do "Import data from the file" and use the same .mif file used for ROM init:
Red numbers shows the differences. Then "Write data to in-system memory", read it back again, and "Import data from file" again:
As you can see, all numbers which were red, now are consistent with actual .mif file.
1. MIF files were generated only once. I don't change them. They are constant. It's irrelevant how they are maked, because they don't change.
2. I have 2 projects in Quartus (13 sp1 web version) - one for master, and one for slave.
3. In both projects I've created "ROM 1-port" megafunctions (1 for master, and 2 of them for slave) and set according .mif files as init values. Like this:
4. Compiled (or fully recompiled) both projects, so the result is two .sof files.
5. Used convert programming file tool to create .pof file:
6. Used programmer to write EPCS:
Here is the quartus log (one of the million attemp to get it to work). Verification also always passes (if enabled).
Info (209060): Started Programmer operation at Tue Jun 21 17:23:18 2022
Info (209018): Device 1 silicon ID is 0x14
Info (209044): Erasing ASP configuration device(s)
Info (209024): Programming device 1
Info (209018): Device 1 silicon ID is 0x14
Info (209011): Successfully performed operation(s)
Info (209061): Ended Programmer operation at Tue Jun 21 17:25:47 20227. Power up/reset the board. Both devices loads its content from EPCS.
8. Nothing works because of broken ROMs content in the slave (and ONLY in the slave). Look at the previous post, I've described there how to detect those errors.
9. Reload the slave .sof via JTAG. Or both master and slave. No changes, ROM still has errors.
10. Reload ROMs via ISCME. No errors.
I want to empasis the problem - .mif files used for ROM initialization in project don't get in ROMs intact. And this problem exists only for slave.
