I have trouble in configure my Cyclone IV E FPGA, (The smallest FBGA 256 commercial variant speed grade 8), using the AS, Active Serial programming method.
Here are the implementation details:
- Using a EPSC128 SPI configuration device. (+3.0V Vcc) and USB Byte Blaster. The Quartus II programmer detects device ID(0x18) and the SPI Flash gets correctly programmed according to the programmer GUI.
- The FPGA MSEL[2..0] pins are put as spec. to . Configuration pins pulled up/down according to spec. except the nSTATUS signal.
- The 3.0V Vcc ramp up time is ~ 1.0 ms.
When I’m measure with my oscilloscope I can see that the FPGA configuration cycle never initiates. The FPGA should set the nCS logic low and start the DCLK but that never happens.
One thing I have noticed is that the nSTATUS pin is NOT pulled up. The spec. states it should. From what I understand from the spec. the nSTATUS toggles to indicate that the FPGA POR is released. (Power Supplies ramped up and are stable). Is this nSTATUS signal just a signal that you can monitor or must it indeed be pulled up.
I have another type of circuit board, (a Cyclone IV E and the same SPI Flash), and I moved away the nSTATUS pull up resistor on that board. Still it is no problem to configure the FPGA from the SPI Flash, so I am little bit confused about the need of nSTATUS pull up resistor or not.
Anyone else, of all you good engineers out there, that have had this issue?
Thank you for contacting Intel community.
Per my understanding, you are having problem with Cyclone IV configuration. Did you follow the configuration guidelines?
Refer to chapter 8 in the link below;
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