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Cyclone IV FPGA PLL power have 2 components
1. Analog - VCCA (2.5V) 2. Digital - VCCD_PLL (1.2V) Powerplay power analyzer reports & board measurements (GX development) shows static current as 34mA for analog supply (VCCA) even when PLL is not in used in design. Why PLL static power is so high ? Is there any way to shut off the static power. Thanks, NLink Copied
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Both supplies have to be powered even if the PLLs are not used. Refer to the pin connection guidelines:
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/cyclone-iv/pcg-01008.pdf- Mark as New
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Thanks rsefton. I got it.
I also see increase in static power by enabling more PLLs in the design. Is this an expected behavior? Regards, N
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