Short answer - Yes. However, there are a few restrictions...
The voltages you specify suggest you'll have at least on single ended clock. From the 'Recommended Operating Conditions for Cyclone IV GX Devices' table in the
data sheet (
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-53001.pdf):
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The CLKIN pins in I/O Banks 3B and 8B can support single-ended I/O standard when the pins are used to clock left PLLs in non-transceiver applications.
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For future reference - Quartus will (usually) answer these questions for you. Try it by putting a small project together, run it through the tools and look at the results. Quartus will always tell you yes or no.
Cheers,
Alex
