Cyclone IV - LVTTL causing FPGA to reset

[Michael-C]

I am using a Cyclone IV FPGA with a Nios Core. I have 22x LVTTL PIO defined to remain tristate and drive low when active. The VCCIO of the bank on the FPGA is tied to +3.3V.

This PIO is connected to a solid state relay cathode though a 1.91K ohm resistor and the anode is tied to +5V.

I have two of the PIO operating as normally. Many of the others, when the PIO goes low, the FPGA reboots. I have been in contact with support, case/thread 06107028 and it has been determined that my configurations are all in-order. They suggested I post something here for futher support.

[Farabi]

Hello, please reply our request in email.

regards,

Farabi

[AqidAyman_Intel]

Hi,

I have taken a look at your schematic that shows the connection between the GPIO and the solid-state relay. So far, there is no difference between all the connection, so it is kind of strange why there is working one and failed one whenever the GPIO give the output low.

How about the parameter settings of the PIO? Are there any differences?

[Michael-C]

All of those PIO are set the same and use the same type of logic. They are normally set to a 'Z' or tristate. When they need to be active, they are set to a '0'.

Remembering the implemented design:

1. The VCCIO bank of the FPGA is tied to 3.3V.

2. Assuming 1.2V forward voltage drop of the solid state relay:

     2.1 with the 330 ohm resistor that is approx 11mA of current into the PIO.

     2.2 with 1.9K ohm resistor that is approx 2mA of current into the PIO.

A few questions come up:

1. Why does the FPGA restart when it tries to drive low?

2. Is the 11mA too much current for the device to handle? 

     2.1. If the 11mA is too much, could it have damaged the device?

         2.1.1 Would the damage be localized to the PIO or the entire bank?

[FvM]

11 mA doesn't overload MAX10 IO. It's however no good design to connect anodes to 5V, IO voltage in off state potentially exceeds maximum ratings.

Curiously, both threads don't consider the possibility that solid state relay output switching causes the reported effects.

[Michael-C]

Its a Cyclone IV device.

The solid state relay in-essence is a forward bias LED with approx 1.2V forward voltage drop which is not an indictive load.

I have used this design on many other boards using different Altera FPGAs and CPLDs with the same solid state relay. None of them have operated in this fashion. 

The only difference in this design is the +5V to the anode as opposed to +3.3V. Will the +5V on the GPIO with it in tri-state mode damage the device?

What will cause the FPGA to reboot itselt?

[AqidAyman_Intel]

When you mentioned the FPGA reboot, you meant the NIOS II getting reboot only and not the whole FPGA including the I/O right?

Have you check the scope shot from the waveform of the output switching whether it has a smooth transition or a lot of spikes coming in?

Also, which two PIO that you said it is working normally?

[AqidAyman_Intel]

Hi,

I wish to follow up with you regarding this issue.

Any updates from your side?

Regards,

Aqid

[AqidAyman_Intel]

As we do not receive any response from you, this thread will be transitioned to community support.

[Michael-C]

I'm not sure how to distinguish between FPGA vs Nios Reboot. When I enable one of the effected PIO, the embedded program re-starts from the beginning. The program has been loaded into the local EEPROM, which is what runs upon startup.

I have monitored the power lines with an oscilloscope to see if there are any dips from the power supply (voltage regulators, etc), and there is none.

I don't recall which of the PIO are operating properly, other than two of all of them.