Cyclone IV: Pll input clk

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Cyclone IV: Pll input clk

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Hello,

I need to know if it is possible to select as pll input a clk signal with a duty cycle different of 50%/50%. Could this imbalance influence the properly generation of pll outputs?

Thanks in advance.

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