Hello,
For FPGA 5CEBA7F27C8N, LVDS Interface to be implemented.
Use Case: Considered 6A Bank for LVDS Implementation. Provided 2.5V operating voltage for Bank 6A.
In Quartus Prime Pin Planner tool, when assigned the I/O standard as LVDS for 6A bank pins, tool is showing error as below for all the differential pair pins assigned.
Error Message " Cant Place Differential I/O positive pin at Differential I/O negetive location".
What does this error indicate? Does any settings to be made in pin planner tool?
Note: FPGA Transmitting Differential pair Signals assigned positive to positive and negetive to negetive as per pin description/pin connection guidelines document.
