Cyclone V 5CEBA7F27C8N LVDS Interface Design

[ShivaKi]

Hello,

For FPGA 5CEBA7F27C8N, LVDS Interface to be implemented. 

Use Case: Considered 6A Bank for LVDS Implementation. Provided 2.5V operating voltage for Bank 6A.

In Quartus Prime Pin Planner tool, when assigned the I/O standard as LVDS for 6A bank pins, tool is showing error as below for all the differential pair pins assigned.

Error Message " Cant Place Differential I/O positive pin at Differential I/O negetive location".

What does this error indicate? Does any settings to be made in pin planner tool? 

Note: FPGA Transmitting Differential pair Signals assigned positive to positive and negetive to negetive as per pin description/pin connection guidelines document.

[AqidAyman_Intel]

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[AqidAyman_Intel]

Hi,

Can you share the steps taken for you to do the pin assignment for those differential pins in your design?

Please also provide the snapshot of the Pin Planner. It may help me to understand the cause.

Regards,

Aqid

[AqidAyman_Intel]

Hi Sir,

I wish to follow up with you. Do you have any more concerns for this issue?

Do you need more support/help?

Regards,

Aqid

[AqidAyman_Intel]

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