Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20640 Discussions

Cyclone V: 5CEBA9F31C7 timing issue for high speed ADC

Altera_Forum
Honored Contributor II
943 Views

I encounter timing issue when I do costraint for high speed ADC. 

the ADC's sample clock rate is 40MHz,resolution is 12bit. 

There is 8 channels for each ADC.(the device is AD9279) 

the speed rate between ADC and FPGA is 480mbps,and the dclk is 240MHz. 

The I/O timing constaints cannot be met for the clock delay is too huge. 

I watch the route path by chip planner and find that the clock takes a detour. 

I have tried to resolve the problem by many ways,like to change parameter of the filtter, 

but it is useless. 

So how to resolve the problem.
0 Kudos
0 Replies
Reply