Remote Update, Serial Flash controller, and Clocks

Altera_Forum · ‎03-29-2016

Hi,

I'm using a Cyclone IV (EP4CE30F23C7), and included in the design is one NIOS II/e processor. The FPGA is configured on power-up from an on-board EPCS16 serial flash (technically Spansion S25FL216K0PMF104) that works well.

I've recently migrated from Quartus II 13.1 up to 15.1.

I want to add both these features to the design:

[a] write & read some non-volatile application settings information in the flash memory

I've planned to use the Serial Flash Controller Core (altera_avalon_epcs_flash_controller), listed in Part 5 of the embedded peripherals ip user guide (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_embedded_ip.pdf). When I moved to Quartus II 15.1, the IP upgrade tool appears to have now named it the "Legacy EPCS/EPCQx1 Flash Controller".

[ b] implement a remote upgrade

I've planned to use the Altera Remote Update (altera_remote_update). Preferably I'd have a bare-bones factory configuration to handle the reconfig to the application code as described in the remote update ip core user guide (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_altremote.pdf), but it's not necessary. An option to only update on the Nios II software instead of complete HW configurations including Nios II software would be nice, but complete-configurations-only if simpler is also fine. FWIW, the application code would receive the data from a UART (UART/USB converter) attached to a PC.

A few questions have come up while I've tried to get the SoC organized:

q1) Is that the best selection of IP under [a] and [ b] above to fit my goals? Is there significant overlap among these that I should only need ONE of them?

q2) The documentation for the altera_avalon_epcs_flash_controller embedded IP says the serial flash interface is not autowired for the Cyclone IV (and III), so it describes how to assign the pins (including DCLK, mentioned below) as regular I/O for use with this IP. Conversely, the altera_remote_update itself doesn't appear to expose any device pins for the top level design to be assigned in the Pin Planner, so does it get auto-wired by the compiler to talk to the EPCS? I'm curious why one of the IP blocks needs to be wired manually, and the other is auto-wired. Perhaps it's because the altera_remote_update uses dedicated hardware?

q3) Does the altera_remote_update core actually handle the read/write at the serial flash?

q3) Is there any conflict then with using both these IP blocks at the same time? Or should they be exclusive: the serial flash controller only be in my application config, and the remote upgrade IP only be in my factory config?

q4) Clocks:

I have a 54MHz global clock fed by an external oscilator that I've been using in early designs so far. The application software itself doesn't do anything intensive that needs a high clock speed, FWIW.
The Remote Update IP Core recommends an fmax of 20MHz.
The "configuration and remote system upgrades" section of the cyclone iv handbook (https://www.altera.com/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51008.pdf) says a 40MHz internal oscilator for DCLK, or use an external clock
Qsys warns that JTAG UART requires "at least 50MHz to operate properly".

So I need a clock max 20MHz for remote update, and min 50MHz for JTAG UART (and by extension, also would be the clock for the CPU I would think). Do I need to supply two clocks to the NIOS system then? If I connect a slower clock to the remote IP core, does it play nice with a CPU running at a different speed?

q5) Is there a suitable reference design that I could review?

Thanks in advance for any advice and comments. I can't find a clear answer or example to clarify these issues so far.

Thanks,

Eric

Altera_Forum · ‎04-07-2016

Hi folks,

Is there any extra detail I can provide?

I've also seen in Qsys that altera_epcq_controller is available, so I suppose that IP could be inserted in place of the altera_avalon_epcs_flash_controller (Legacy EPCS/EPCQx1 Flash Controller)in the original questions.

Cheers,

Eric