I have a card with aCyclone V that is using Active Serial Configuration from a Micron N25Q(128Mbit) flash.Recently i have hadto switch flash to Micron MT25Q, due to the fact that N25Q is end-of-life. The problem I havenow is that the FPGA on some of my boards does not configure, whereas it isalways configuring ok on other boards. On the boards thatdo not configure properly, the configuration works ok if I put a probe on theflash clock, or if I solder on a 10pF capacitor between the flash clock andground, or if the board is warmed up. So it seems to be atiming problem on the interface between the flash and the FPGA. The FPGA is clockingdata out on the falling edge of the clock, and in on the falling edge of theclock. The flash isclocking data out on the falling edge of the clock, and in on the rising edgeof the clock. The clock frequencyis 9.8 MHz, so there should be no problem meeting setup times. However, there couldbe a problem with hold time on data going from flash to FPGA, given that datais clocked out on falling edge from the flash, and clocked into the FPGA on thefalling edge. But - the clock iscoming from the FPGA, the flash has a clock to out of at least 1.5ns (measuredvalue in lab is 2-2.5ns), and the FPGA has a hold time of 0ns, according to theCyclone V data sheet. The clock looksbeautiful - perfect flanks, very little noise. There is no noise onany of the power rails. When the FPGA is notconfiguring, I see that CONF_DONE stays low, but nSTATUS is pulled low every~3.7ms. I'm familiar withthis very nice thread: https://alteraforum.com/forum/showthread.php?t=56762&page=4. This thread hastempted me to use Windbond flash instead of Micron, but I'm concerned that thismay not improve my situation. After all, theproblems I'm having is only on some of my boards, not on all of them. I'm also aware thatAltera has recently added support for Micron MT25, but unfortunately this onlyapplies to 256Mbit and above, and at the moment these devices are hard to get. So, I'm reaching outto all of you experts in this forum; do you have any suggestions, ideas,thoughts, comments?
Even if this is an very old message:
I came across this, because I have exactly the same issue: Cyclone V soc with MT25Q
Traces are quite short (D0-D4: 16-20 mm; DCLK 18mm).
On some boards the AS config fails. As soon as I touch the DCLK (when trying to measure where the issue may be) the configuration is successful.
I also assume a timing problem but cannot find any setup or hold timing issues.
How was this problem solved? I would be more than happy to get a hint.
Thank you very much
I also came across some problems using the MT25QL256 as configuration device for CYCLONE V.
I found out, that the configuaration fails, when the board is cold - lets say 0°C and below (the exeact value I cant say).
Then one can also observe that the nSTATUS pin toggles H to L repeatedly as an indicator that the FPGA can't load its configuration error-free out of the FLASH and repeats that process.
With rising temperature the repetition rate goes down and at some certain temperature the configuration process is done without errors.
For my opinion, this hints to a timing problem too.
Did you guys find any solution for the problems you described?
It would also be nice, if some INTEL professionals could state something here...
Best regards, Marco.
I did find my timing issue. Pretty wired but simple if you read the right documents. I can recommend "AN 822: Intel® FPGA Configuration
Device Migration Guideline".
There you should check the tDH (data hold timing). The clock line has to be absurdly long, or the clock has to be delayed in another way.