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Default parameter value override on netlist file

G_Sunil_Kumar
Beginner
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Hi,

I have a Verilog design with default parameters. During RTL synthesis with Quartus tool, I could able to override these parameters and run synthesis successfully.

But if I try to run synthesis with a netlist file (.qxp) and try to override the default parameter values, the synthesis tool throws out error. Am I doing something wrong? Pl. suggest.

thanks,

sunil 

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