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Altera_Forum
Honored Contributor I
1,036 Views

Cyclone V Clock Not Toggling

Device: 5CGTFD9E5F35C7 

Quartus Version 14.1 

 

I am currently having problems with the on-board oscillator (CLK5p(U31)) not toggling when used as the clock source in Signal Tap(e.g. the 'waiting for clock' status). In my design this clock is only connected to a Qsys generated DRAM module. The outputted Avalon clock also does not toggle which is a result of the input clock not toggling. I have tried using different clocks such as the CLK10p from the X4 programmable oscillator and that did not produce the waiting for clock status from Signal Tap. But, this clock did not produce an Avalon clock that toggled. I also tapped the waitrequest_n(1 = bus can be accessed) output from the dma_module and that did not toggle. However, this is probably due to the internal clocks of the DRAM module not being generated for some reason. I have also made a simple counter and viewed the results with Signal Tap to test the clocks. I found that clocks from sourced from the programmable X4 clock work as predicted. However, the fixed oscillators such as CLK5p do not oscillate and give the 'waiting for clock' status.  

 

I also verified that the Qsys module is configured for input clock frequency (125 MHz).  

 

Also DRAM timing was not met for some address values. The input clock and DRAM clock output also have negative slack (-4.570 and -.470 respectively). 

 

Any help would be greatly appreciated.
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4 Replies
Altera_Forum
Honored Contributor I
58 Views

What kind of external clock are you providing to your device and on what pin(s) is it connected? 

 

Your comment about 'on-board oscillator CLK5P not toggling' implies to me you think you don't need an external clock source. 

 

The Cyclone V does not have an internal clock oscillator so you need to provide an external signal (typically 50MHz or 125MHz).
Altera_Forum
Honored Contributor I
58 Views

I was using the terminology provided in the documentation. I attached a picture of the documentation. So when I use the CLK5p(Pin U31(p) Pin U30(n)) driven from source X5 is does not toggle when I examine my design in Signal Tap giving me the 'waiting for clock' status.

Altera_Forum
Honored Contributor I
58 Views

So you're using a dev kit. I think that was the confusion. How do you have the clock connected to Signaltap? Is the clock going through a PLL or are you tapping the input clock pin directly?

Altera_Forum
Honored Contributor I
58 Views

I've tried both. I originally tapped the DRAM signals with the outputted clock which is a PLL(ref clock is CLK5p) output. But, since that outputted clock was not toggling I tried using the input clock directly and I received the same results. I recently connected another clock (CLK10p, references programmable clock X4) which caused the outputted DRAM clock to toggle. However, I cannot write to the DRAM because the bus waitrequest indicates that its busy. I have tried resetting as well as attempting to write to the bus even though waitrequest indicated busy. Those both did not allow any valid writes or reads and did not toggle the bus wait request.

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