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Clock Data Recovery in Stratix V Transceiver

Altera_Forum
Honored Contributor II
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Hello, 

 

I'm working on a project where I'm using the Transceiver of Stratix V and it is operating at 2 Gbps. I'm trying to use the Clock Data Recovery (CDR) in Lock to Data (LTD) mode but the output is not as expected. It works fine when using Lock to reference (LTR) mode. In LTD, I'm asserting the rx_digitalreset signal after rx_is_lockedtodata stops toggling but it doesn't want to work properly. 

 

So, what should I do? How can I make it function correctly? 

 

Thanks
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Altera_Forum
Honored Contributor II
129 Views

 

--- Quote Start ---  

 

So, what should I do? How can I make it function correctly? 

 

--- Quote End ---  

 

Simulate it. Look at the first few documents here for instructions:  

 

https://www.ovro.caltech.edu/~dwh/correlator/cobra_docs.html 

 

The Arria V GZ part uses the Stratix V transceivers.  

 

Cheers, 

Dave
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