Dear folks,I'm currently designing a Cyclone V DDR3 Ram interface with a single component DDR3L using the hard memory controller. In EMIF handbook I find, that for clock < 933MHz no package deskew is required, I think thats way beyond Cyclone V anyway. However, the emif handbook tells that signals should be routed to be time matched to a maximum skew of 20ps. But when I have a look at the net-length/delay Excel Sheets for the Cyclone V 5CEFA2F23 I find difference in delays for the pads of about 100ps (e.g. DQ0 vs DQ3). So how does it come that I should keep the skew below 20ps when routing while the package itself already has a skew of about 100ps. Doesn't it make sense to account for the package skew even if I'm going to run with about 400MHz clock only? For me it really doesn't cost a lot to account for the package skew as well when routing and I think it will improve the signal quality a lot. Can I use the Excel sheets values for package deskewing or does this break things? Quartus Megawizard doesn't shows me the "Package Deskew Option" for my design, so I get no deskew information from Quartus. cheers, Andreas
Hi Andreas,Yes, it is true that some package length is more than 100ps. Anyway, do not worry on that. Quartus timequest will make the timing analysis based on the package length. What user have to achieve is to meet the 20ps on the board trace matching. Enter those board parameters into GUI , generate the IP and see it the full compilation close timing. For more information, Cyclone V UniPHY do not support package deskew. What user have to achieve is to meet the board design guideline and let quartus handle the package skew different in timing analysis. Hope this helps. (This message was posted on behalf of Intel Corporation)
Hi, I was wondering about lines length in the SODIMM flat mounted PCB connector. I think lines of this connector is different in length between sides, am i wrong? Do I need to deskew this difference on PCB traces too?