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Honored Contributor I

Cyclone V DMA/DRAM Issues


Cyclone V GT Development Board 


I am trouble interfacing with the on-board DRAM using the Avalon bus. I have attached the file used for testing. 


When trying to access DRAM the signal waitrequest_n(indicating the memory controller is busy) never goes high, even on initialization. I have verified that all pin assignments are correct and the memory is configured correctly in QSYS. I have tried asserting a write even though the bus is busy, as recommended by the Altera documentation. However, that did not work and the waitrequest_n signal did not go high. 


Another user has tested the board before me and verified the functionality of DRAM. 


I have also attempted to use the board test system and that does not give me results. I programmed the board using Quartus 14.1 manually and used the provided Signal Tap file. The signal tap gave me 'waiting for clock status' indicating the clock was not toggling. I changed the default clock to one of the programmable oscillators. That also did not work. 


So my question is am I missing something major or is it likely that the board is malfunctioning.
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