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Hello,
the dev board i have is the DE0-Nano-SOC
5csema4u236cn
I am looking for an easy and fast way to give the HPS access to the GPIO pins. Currently I have this flow setup:
1. click button on webpage
2. hps saves button state and sends a 1 to the FPGA DigitalOut_1
-(HPS) int A =1 -> H2F word -> (FPGA) DO_1 = 1 ( takes 1000ms)
3. external hardware sends a high signal 150ms after recieving 1
4. FPGA recieves the high signal on DigitalIn_1 line, sends a word back to HPS
- (FPGA) DI_1 = 1 -> F2H word -> (HPS) int B = 1 (takes 1000ms)
the problem is that sending signals across the F2h and H2F bus is way too slow. Is it possible for the HPS to directly access and control the DigitalOut/In pins?
My current issue is that the F2h and H2b bus is way too slow. Is there a way for the HPS to directly access the I/O pins?
the digital pins are connected to a pcb that sends a trigger back if it sees a high signal. the trigger only lasts for about 20ms and is usually missed in the F2H window.
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You don't have to use the bridges to access GPIO. Set up GPIO access in the parameter editor for the HPS.
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Hello sstrell.
I must have a misguided understanding of how this works. Could you possibly point me in the direction of a doc or video that would explain how I would go about that?
Under Quartus->Qsys, I only see the F2h and H2F interfaces. Would the configuration you're referring to be there?
Or do you mean that I need to map the FPGA I/O to a spot in memory for the HPS to access?
side note..... : FPGA is programmed in Quartus(Verilog) and HPS in eclipse (C++).
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No, this is in the IP parameter editor for the HPS in Platform Designer in the pin mux settings. Click the GPIO button to make a dedicated HPS pin act as GPIO.
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Hi,
You can assign directly HPS IO from HPS Bank IO_A and IO_B and select as the GPIO in platform designer tool.
Regards
Tiwari
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Hi,
Let me know if you have any other query on this.
Regards
Tiwari
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