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Cyclone V FPGA configuration

Jpascal
Beginner
1,104 Views

Hello,

My platform configuration :

  • Cyclone V SoC FPGA
  • ECPQ memory connected to FPGA through AS
  • MSEL pins set to use AS configuration scheme

I store a FPGA configuration in EPCQ memory. While booting, FPGA is configured through AS link.

The question is :

Is it possible to reconfigure FPGA (with a new configuration and without changing MSEL pins setting) through HPS while functionning ?

 

In Cyclone V Device Handbook Volume 1, I found out that MSEL pins are sampled during Reste state execution :

Jpascal_0-1688118044839.png

And in Cyclone V HPS Reference Manual, I found this :

Jpascal_1-1688118116395.png

Does it mean that FPGA Manager always starts by executing Reset state when configuring FPGA ? Regardless of the fact that it is processing full reconfiguration or partial reconfiguration ? Am I missing/misunderstanding something in the documentation ?

Thanks for the help

 

 

 

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sstrell
Honored Contributor III
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Once the processor is booted, it can be used to program the FPGA part of the device at any time.

View solution in original post

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sstrell
Honored Contributor III
1,085 Views

Once the processor is booted, it can be used to program the FPGA part of the device at any time.

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Jpascal
Beginner
1,038 Views

Hello,

Thanks for the answer.

Is it regardless of MSEL pins setting ?

If so, where did you get the information ?

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sstrell
Honored Contributor III
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MSEL pins: not sure why you're thinking they would be an issue.  They are obviously set in hardware before power on.  What is your concern with them?

I get the information from my experience working with the devices, documentation, and training.

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/fpga-configuration-79225.html

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Jpascal
Beginner
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I thought MSEL pins were an issue because my setting is not one of those described in the link of your answer (It's not FFP because FPGA is first configured on power-on from an external device connected through AS). What causes me trouble is the second and entirely new  configuration that should be done by HPS.

I understood that when using HPS to configure FPGA, FPGA manager resets the FPGA. Since MSEL pins are sampled during Reset phase and since my MSEL pins setting is not a HPS configuration scheme, I thought that trying to configure FPGA by HPS would not work.

I guess I got it wrong seeing your answer and Fakhrul answer.

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Fakhrul
Employee
977 Views

Hello Jpascal,


Indeed, sstrell's statement is reasonable. The MSEL pins should not pose any problems.


Regards,

Fakhrul


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Fakhrul
Employee
923 Views

Please be advised that due to the absence of a response from you regarding the previous notification we provided, we will be transitioning this thread to community support. If you have any new questions or concerns, we kindly suggest opening a new thread to receive assistance from Intel experts. However, if you do not have any further inquiries, the community users will be available to assist you on this thread. Thank you for your understanding.


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