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Altera_Forum
Honored Contributor I
1,448 Views

Cyclone V Fractional PLLs don't output expected clock frequency

I'm using Quartus 17.0.2. I have trying to generate a 148.5MHz clock with a 50MHz input reference clock. When I put the PLL in fractional mode and enter 148.5M as my target frequency the megawizard states that it can achieve the exact frequency of 148.5MHz and provided no warning message about not being able to get the exact clock rate. (See attached image.) 

 

However, when I look at the STA report I see that the actually frequency of the clock is 148.53515625MHz. 

And the multiply/divide values are as follows: 

 

For VCO: 

Multiply= 4563 

Divide = 512 

For Clock output: 

Multiply = 1 

Divide = 3 

 

Why is the PLL telling me that it can achieve my exact frequency when it's really not?? 

 

The frequency observed in hardware on an oscilloscope is indeed about 148.54MHz which is not what I specified in the megawizard. 

 

What makes this even worse is that a VCO multiply value of 4562 would actually generate a frequency closer to what I requested (even though not exact). So that's pretty bad behavior for the tool.
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8 Replies
Altera_Forum
Honored Contributor I
125 Views

The reported parameters are integer rather than fractional parameters. It looks like Quartus 17 doesn't manage to implement a fractional PLL.

Altera_Forum
Honored Contributor I
125 Views

Have you read this page ( https://www.altera.com/support/support-resources/knowledge-base/solutions/rd08062012_921.html ) and the document it points to ? 

 

One of the issues is you don't check the 'Enable Physical Output Clock Parameters' check box in the wizard.
Altera_Forum
Honored Contributor I
125 Views

 

--- Quote Start ---  

One of the issues is you don't check the 'Enable Physical Output Clock Parameters' check box in the wizard. 

--- Quote End ---  

 

 

I'm not sure what that has to do with it generating the incorrect frequency. There are two options to generate an output clock frequency: 

 

1) Enter the frequency you want and the megawizard will calculate the proper M/N/etc parameters for you. This is when the 'Enable Physical Output Clock Parameters' box is UNCHECKED. 

 

2) Enter the M/N/etc parameters yourself and the megawizard will tell you the resulting frequency. This is when the 'Enable Physical Output Clock Parameters' box is CHECKED. 

 

The document that you linked to simply shows the option# 2 approach to configuring the PLL.
Altera_Forum
Honored Contributor I
125 Views

 

--- Quote Start ---  

There are two options to generate an output clock frequency. 

--- Quote End ---  

 

Yes, the physical parameter options should be used if you are not satisfied with the automatically generated parameters. 

 

The point is that previous Quartus versions, e.g. Quartus 13.1 which I use for existing Cyclone V projects, seem to generate useful fractional parameters automatically. But the reported parameters in your post# 1 suggest, that Quartus 17 generated an integer PLL although a fractional PLL was intended.
Altera_Forum
Honored Contributor I
125 Views

So I entered the physical parameters manually and it said it could achieve a frequency of 148.4999999MHz. I'm fine with that. 

 

So I tried to synthesize the design and I am getting an absolutely bizarre synthesis error: 

 

Error (13305): Verilog HDL error at altera_pll.v(2163): can't find port "refiqclk_1" File: c:/altera/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 2163 

 

This isn't even one of my source files!! O.o 

 

I have attached the file that the megawizard generated. I'm not sure what else to say...how can I compete with source files errors in Quartus' own installation directory..........?????
Altera_Forum
Honored Contributor I
125 Views

 

--- Quote Start ---  

So I entered the physical parameters manually and it said it could achieve a frequency of 148.4999999MHz. I'm fine with that. 

 

So I tried to synthesize the design and I am getting an absolutely bizarre synthesis error: 

 

Error (13305): Verilog HDL error at altera_pll.v(2163): can't find port "refiqclk_1" File: c:/altera/17.0/quartus/libraries/megafunctions/altera_pll.v Line: 2163 

 

This isn't even one of my source files!! O.o 

 

I have attached the file that the megawizard generated. I'm not sure what else to say...how can I compete with source files errors in Quartus' own installation directory..........????? 

--- Quote End ---  

 

 

This looks like an altera library problem. I looked at the same file in my 16.0 install, and I see in the altera_pll.v file: 

 

altera_cyclonev_pll# ( ... ) cyclonev_pll ( ... // cyclonev_pll_refclk_select pins .adjpllin(adjpllin), .cclk(cclk), .coreclkin(), .extswitch(extswitch), .iqtxrxclkin(), .plliqclkin(), .rxiqclkin(), .clkin({2'b0,refclk1, refclk}), .refiqclk_0(), .refiqclk_1(), .clk0bad(clkbad_wire), .clk1bad(clkbad_wire), .pllclksel(activeclk_wire), // cyclonev_pll_reconfig pins  

 

so it expects refiqclk_0 and refiqclk_1 to be two separate one bit wide ports. But in the referenced altera_cyclonev_pll.v module file I see: 

 

module altera_cyclonev_pll( ... clkin, // 4 refiqclk_0, // 2 ... ); ... input clkin; input refiqclk_0; ...  

 

that refiqclk_0 is a single port that is two bits wide, and refiqclk_1 is a port that does not exist. So there is an inconsistency/error in the base altera library definition files. So it would appear that anybody that has tried to use a fractional PLL in a CycloneV would be getting this error, at least in 16.0 and thru 17.0.2. 

 

This is a problem altera needs to fix. However, in the short term one could probably just comment out the reference .refiqclk_1(), on line 2163 of file altera_pll.v as a quick fix, as the ports are not connected and in this context do nothing useful.
Altera_Forum
Honored Contributor I
125 Views

 

--- Quote Start ---  

in the short term one could probably just comment out the reference .refiqclk_1(), on line 2163 of file altera_pll.v as a quick fix, as the ports are not connected and in this context do nothing useful. 

--- Quote End ---  

 

Yep, I actually tried that already. The design will actually elaborate, however just before synthesis finishes is spits out about 100 different syntax errors related to other altera library modules. This is a mess!!
Altera_Forum
Honored Contributor I
125 Views

 

--- Quote Start ---  

Yep, I actually tried that already. The design will actually elaborate, however just before synthesis finishes is spits out about 100 different syntax errors related to other altera library modules. This is a mess!! 

--- Quote End ---  

 

 

Sounds like you need to file a support request with Altera to inform them their software has a problem ....
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