Cyclone V GX evaluation kit question

[Altera_Forum]

Hi, 

I want to use the Cyclone V GX PCIe evaluation kit (http://www.altera.com/products/devkits/altera/kit-cyclone-v-gx.html). I need to design a daughter board that will connect to the FPGA via the HSMC connector and I need as much GPIOs as possible. Note that the daughter card will use 3.3V logic hence I will use a voltage translator IC to work with the evaluation board (that uses 2.5V logic).  My question is about the connector - according to the reference manual pins H14 and J14 (pins 33, 34 of the J1 HSMC connector) are Management serial data/clock. What does it mean? Can I use them as GPIOs? Can I use J19 (dedicated CMOS clock out) as a GPIO?   Thank you

[Altera_Forum]

You need to download and install the kit documentation. The schematic should be in there somewhere. Go and have a look at it to see what those pins connect to. 

 The HSMC specification defines a 'recommended' pin out for the connector. The Management bus is just an I2C interface. Its likely that its just connected to GPIO pins on the FPGA. There might be a pull-up to 3.3V. The GPIOs pins might be in a 2.5V bank. For an I2C application, they would have only been driven low, and the 3.3V pull-up would have generated the high. If that is true, then you can drive these signals high or low (the high will be whatever the bank VCCIO is). If you need to receive 3.3V, then you should review the handbook regarding maximum voltages.  The same comments apply to the CMOS clock out pin - if its connected to a GPIO, then you can use it as you like.  The reason for the HSMC specifying those pins with a particular function or direction is that it allows daughter card manufacturers to implement their hardware to adhere to the spec. When you're developing your own daughter card for a specific FPGA board, you just need to make them compatible. Note that you might not be able to use your board with another development kit, so try to keep things compatible if you think you might want to use your daughter board with a different kit, eg., put some series resistors in the path between your daughter card signal driving the CMOS clock out pin on the HSMC, so that you can isolate your daughter card driver from the CMOS clock out driver on a different kit.  Cheers, Dave

[Altera_Forum]

Hi Dave, 

I've downloaded the kit documentation and the schematic. In the schematic the pins are indeed connected to GPIOs, the only thing that concerned me is that in the manual it says that these are management pins and not GPIOs. Now I understand that I can use them as GPIOs. As I mentioned earlier I'll need to use a voltage translator in order to work with 3.3V logic (correct me if I'm wrong). It would be nice if the evaluation board had an option to change the IO voltage,  Thank you for your help.

[Altera_Forum]

--- Quote Start ---   As I mentioned earlier I'll need to use a voltage translator in order to work with 3.3V logic (correct me if I'm wrong).  --- Quote End ---    You need to review the Cyclone V data sheet for the electrical characteristics of the I/Os.  http://www.altera.com/literature/hb/cyclone-v/cv_51002.pdf   Look at p11, "Table 14. Single-Ended I/O Standards for Cyclone V Devices", note that a 2.5V I/O bank has a VIL(max) = 1.7V and VIH(max) = 3.6V.  Look at p3, "Table 2. Maximum Allowed Overshoot During Transitions for Cyclone V Devices", the 100% duty cycle limit is 3.7V.  According to these parameters, you can drive the 2.5V logic inputs with 3.3V. So long as your inputs are "well-behaved" (no overshoot or ringing that violates Table 2), then you do not need buffers.  That being said, it is sometimes "better to be safe than sorry", so its your call.  Cheers, Dave

[Altera_Forum]

Thank you for pointing that out. Indeed that means that I don't need voltage translator. My signals are going to be "well-behaved". I think that in this case a voltage translator might do more damage then good. For example it can limit the signals frequency or cause some kind of signal integrity problem. I just need to check that the other side can use 2.5V instead of 3.3V though I'm pretty sure it will be fine. 

 Thank you Dave

[Altera_Forum]

--- Quote Start ---  Thank you for pointing that out. Indeed that means that I don't need voltage translator. My signals are going to be "well-behaved". I think that in this case a voltage translator might do more damage then good. For example it can limit the signals frequency or cause some kind of signal integrity problem. I just need to check that the other side can use 2.5V instead of 3.3V though I'm pretty sure it will be fine.   --- Quote End ---    If you don't use a buffer, then still try to be conservative; add series resistors on each of the signals that go between your board and the FPGA. Stuff them with a low-value (eg., 0-ohms or 10-ohms). You can use these as source terminations on signals configured to drive from your board over to the FPGA board. That'll eliminate ringing/overshoot.  Cheers, Dave

[Altera_Forum]

I think that I'll have the voltage translator as a BOM option. The default will be to use serial resistors as you suggested and the voltage translator option will be a fall-back.

[Altera_Forum]

--- Quote Start ---  I think that I'll have the voltage translator as a BOM option. The default will be to use serial resistors as you suggested and the voltage translator option will be a fall-back.  --- Quote End ---    That's a good idea. Its better to have the buffer on the PCB than 'wish' you had it when you encounter a problem that it could solve :)  Cheers, Dave