Cyclone V, HPS SPI routing to FPGA pins

Altera_Forum · ‎01-13-2017

Hello everyone,

I'm using the DE0-Nano Soc Board and tried to route the signals of the HPS SPI Master Peripheral to FPGA Pins.

In Qsys i activated the SPI Master and set the pins to FPGA. In top_level entity they are connected to fpga pins.

The problem is, that the Fitter isn't able to route the sclk signal to the fpga pin i have assigned. When i don't assign a pin, the fitter can place it to some pin locations.

With assigned pins i get the following error messages.

 
    Error (175020): The Fitter cannot place logic auto-promoted clock driver that is part of Arria V/Cyclone V Hard Processor System soc_system_hps_0 in region (28, 8) to (68, 61), to which it is constrained, because there are no valid locations in the region for logic of this type.
        Info (14596): Information about the failing component(s):
            Info (175028): The auto-promoted clock driver name(s): soc_system:qsys_system|soc_system_hps_0:hps_0|soc_system_hps_0_fpga_interfaces:fpga_interfaces|spim0_sclk_out~CLKENA0
        Error (16234): No legal location could be found out of 30 considered location(s).  Reasons why each location could not be used are summarized below:
            Error (15123): The following auto-promoted clock driver locations cannot route to all the required pins
                Info (175027): Destination: pin fpga_spi0_sclk
                    Info (175015): The I/O pad fpga_spi0_sclk is constrained to the location PIN_AE12 due to: User Location Constraints (PIN_AE12)
                        Info (14709): The constrained I/O pad is contained within this pin
                Info (175029): 11 locations affected
                    Info (175029): CLKCTRL_R0
                    Info (175029): CLKCTRL_R2
                    Info (175029): CLKCTRL_R4
                    Info (175029): CLKCTRL_R6
                    Info (175029): CLKCTRL_R8
                    Info (175029): CLKCTRL_R70
                    Info (175029): CLKCTRL_R72
                    Info (175029): CLKCTRL_R74
                    Info (175029): CLKCTRL_R76
                    Info (175029): CLKCTRL_R78
                    Info (175029): CLKCTRL_R80
            Info (175013): The auto-promoted clock driver is constrained to the region (28, 8) to (68, 61) due to related logic
                Info (175015): The HPS_INTERFACE_PERIPHERAL_SPI_MASTER soc_system:qsys_system|soc_system_hps_0:hps_0|soc_system_hps_0_fpga_interfaces:fpga_interfaces|peripheral_spim0 is constrained to the location HPSINTERFACEPERIPHERALSPIMASTER_X32_Y44_N111 due to: User Location Constraints (HPSINTERFACEPERIPHERALSPIMASTER_X32_Y44_N111)
                Info (14709): The constrained HPS_INTERFACE_PERIPHERAL_SPI_MASTER drives this auto-promoted clock driver
            Error (175006): Could not find path between source HPS_INTERFACE_PERIPHERAL_SPI_MASTER and the auto-promoted clock driver
                Info (175026): Source: HPS_INTERFACE_PERIPHERAL_SPI_MASTER soc_system:qsys_system|soc_system_hps_0:hps_0|soc_system_hps_0_fpga_interfaces:fpga_interfaces|peripheral_spim0
                    Info (175015): The HPS_INTERFACE_PERIPHERAL_SPI_MASTER soc_system:qsys_system|soc_system_hps_0:hps_0|soc_system_hps_0_fpga_interfaces:fpga_interfaces|peripheral_spim0 is constrained to the location HPSINTERFACEPERIPHERALSPIMASTER_X32_Y44_N111 due to: User Location Constraints (HPSINTERFACEPERIPHERALSPIMASTER_X32_Y44_N111)
                Info (175021): The HPS_INTERFACE_PERIPHERAL_SPI_MASTER was placed in location HPSINTERFACEPERIPHERALSPIMASTER_X32_Y44_N111
                Error (175022): The auto-promoted clock driver could not be placed in any location to satisfy its connectivity requirements
                Info (175029): 19 locations affected
                    Info (175029): CLKCTRL_G12
                    Info (175029): CLKCTRL_G13
                    Info (175029): CLKCTRL_G14
                    Info (175029): CLKCTRL_G15
                    Info (175029): CLKCTRL_R1
                    Info (175029): CLKCTRL_R3
                    Info (175029): CLKCTRL_R5
                    Info (175029): CLKCTRL_R7
                    Info (175029): CLKCTRL_R9
                    Info (175029): CLKCTRL_G8
                    Info (175029): CLKCTRL_G9
                    Info (175029): CLKCTRL_G10
                    Info (175029): and 7 more locations not displayed

I think that there are some restrictions which pins the peripherals of the hps can access in the fpga region, but i wasn't able to find something about it in the device handbook.

It's also possible that i haven't the right settings in my project, so have sombody else succesfully placed the spi signals in the fpga region and can give me some tips?

Best regards

Bjoern

Altera_Forum · ‎01-17-2017

I have send an Service Request to Altera and got an answer today.

It seems to be a bug in the quartus software, and the workaround is described here: https://www.altera.com/support/support-resources/knowledge-base/solutions/rd10132014_244.html

Maybe this solution helps someone else in the future.

Altera_Forum · ‎05-29-2017

Hello Captain-Chaos,

I'm facing the same problem while exporting the spi_clk hps signal to fpga and got this error. Did you managed to solve it? I used the workaround posted but the error is still there.

Altera_Forum · ‎05-29-2017

--- Quote Start ---

Hello Captain-Chaos,

I'm facing the same problem while exporting the spi_clk hps signal to fpga and got this error. Did you managed to solve it? I used the workaround posted but the error is still there.

--- Quote End ---

Hey,

in my Design the solution with an boolean combinational function works fine. Did you try this or the maual LUT instantiation?

AN706 (https://www.altera.com/documentation/mwh1410561892049.html) describes the reqired steps to export the perihperals, have you checked that there is no fault in your design?

Altera_Forum · ‎03-13-2018

Just had the same issue (w/ Q16.1) and that did the trick. Thanks for the heads-up on this.