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Altera_Forum
Honored Contributor I
777 Views

Cyclone V: How to generate a Trigger Signal ?

Hi,  

 

Can anyone suggest me, how to create trigger signal for controlling 128 bits counter data ?
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4 Replies
Altera_Forum
Honored Contributor I
63 Views

Hi, 

 

What you want to control with counter? 

Enable can also be used as trigger. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
63 Views

 

--- Quote Start ---  

Hi, 

 

What you want to control with counter? 

Enable can also be used as trigger. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation) 

--- Quote End ---  

 

 

Actually what i am trying to do :( Sending LVDS signal [128 bits counter data] from cyclone V to XILINX Custom Board, and trying to control LVDS signal through trigger in NIOS Processor. I worked in XILINX but i am new to Altera and Qsys. So please help me in this part. I need to try the LVDS signal through trigger via NIOS Processor. How ? ?
Altera_Forum
Honored Contributor I
63 Views

Hi, 

 

You can use on chip memory as register. 

use one of the memory address like register and assign a bit to trigger the counter in a c-code in eclipse design. This bit to be used in you HDL coding to trigger counter. 

(embedded code<->Nios<->On-chip memory<->user logic) 

 

Look into below link you may get some idea. 

http://scale.engin.brown.edu/classes/en2911xf14/qsys_comp.pdf 

 

Let me know if you need any further assistance. 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
SS5
Novice
63 Views

Hello,

 

I am trying to generate Trigger signals and Counter data through Quartus and NIOS.

Verilog code:

module Counter( input clk, input enable, input reset, output reg[31:0] Final_value // output wire trig ); reg[31:0] counter_out; reg [7:0] temp=0; reg [31:0] counter_result; wire temp1; wire temp2; reg trig; always@(posedge clk or negedge reset) begin if(~reset) begin trig<=0; temp<=0; counter_out<=0; end else if (enable==1'b1) begin counter_out<=counter_out+1; temp<=temp+1; if(temp==25) begin temp<=0; trig<=~trig; end   end   assign temp1=trig; assign temp2=temp1&&clk; always@(posedge temp2 or negedge reset) if(~reset) counter_result<=0; else begin counter_result<=counter_result+1; end always@(posedge trig or negedge reset) if(~reset) Final_value<=0; else begin Final_value<=counter_result; end endmodule

 

module Counter( input clk, input enable, input reset, output reg[31:0] Final_value // output wire trig ); reg[31:0] counter_out; reg [7:0] temp=0; reg [31:0] counter_result; wire temp1; wire temp2; reg trig; always@(posedge clk or negedge reset) begin if(~reset) begin trig<=0; temp<=0; counter_out<=0; end else if (enable==1'b1) begin counter_out<=counter_out+1; temp<=temp+1; if(temp==25) begin temp<=0; trig<=~trig; end   end   assign temp1=trig; assign temp2=temp1&&clk; always@(posedge temp2 or negedge reset) if(~reset) counter_result<=0; else begin counter_result<=counter_result+1; end always@(posedge trig or negedge reset) if(~reset) Final_value<=0; else begin Final_value<=counter_result; end endmodule

Enable signal is coming from NIOS through PIO. After receiving the enable bit, code should generate Trigger signal, and at every neck edge (either positive or negative) i need to store the counter data in register.

For above process, i have used AVALON FIFO core, but in NIOS console i am not getting proper counter data. Please suggest me

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