Cyclone V LVDS & DDR3 on same bank

[Altera_Forum]

Hello, 

 I am planning to use a Cyclone V 5CGTFD7D5F31 with the following requirements;  - 32 bit DDR3 interface Top and Bottom (64 bit total)  - 68 LVDS input pairs  Once I have assigned pins to the HMC for the DDR3 interfaces I am left with the following available LVDS RX pairs per bank;  3A: 8  3B: 6  4A: 5  5A: 8  5B: 12  6A: 20  7A: 5  8A: 14  Total: 78  The HMC uses banks 3B, 4A, 7A & 8A, so I will need to have both LVDS and DDR3 signals in these same banks.     Here’s the crunch:  DDR3 requires that VCCIO is set to 1.5V, while LVDS requires that VCCIO is set to 2.5V. VCCPD should be 2.5V in both cases (table 5-1).    From C5 handbook, Vol 2:  Page 5-2; “VCCPD powers the LVDS input buffers”.  Page 5-12; LVDS Input RD OCT; “You can use RD OCT when you set both the VCCIO and VCCPD to 2.5 V.”    So, assuming that the LVDS input buffers are powered from VCCPD = 2.5V, can I use the LVDS differential inputs if VCCIO is set to 1.5V fro DDR3?  Also, can I use RD OCT?   If not, can I do it with external RD?   Any guidance would be greatly appreciated!   Thanks, Ken

[Altera_Forum]

--- Quote Start ---  So, assuming that the LVDS input buffers are powered from VCCPD = 2.5V, can I use the LVDS differential inputs if VCCIO is set to 1.5V fro DDR3? Also, can I use RD OCT?  If not, can I do it with external RD?  --- Quote End ---   The lvds input rd oct paragraph states clearly that Rd OCT requires 2.5 VCCIO. So external 100 ohm termination resistors are required. The statement suggests in return, that the combination VCCPD=2.5, VCCIO < 2.5V (e.g. 1.5 V) is possible. Did you check, if Quartus V11.1 accepts LVDS receivers in a 1.5 V bank?

[Altera_Forum]

Hello FvM, 

Thanks for the suggestion. I have made a simple project with LVDS inputs and set default I/O standard to 1.5V in the “Device and Pin Options” window. Also have 1.5V I/O in the same bank. So looks OK (even works if I use 1.2V).  However what is bothering me is that it also allows me set in the Assignment Editor for the LVDS inputs:   Input Termination = Differential   No errors    Does “Input Termination = Differential” mean that the LVDS receivers have on chip termination enabled?    Thanks, Ken

[Altera_Forum]

Hi, 

 did you already gain any more information about placing a LVDS input at a 1.5V bank? This would be an option in my design too. I tried it with my Arria V and also got no error when compiling this setup. In the device handbook on page 139 the VCCIO voltage for input operation should be VCCPD. Or it only depends on VCCPD as in your understand. Very confusing.  Could someone bring some clarity into this?  Best Regards

[Altera_Forum]

Hello, 

Have not had any further info on this one, but it seems that we need the following: VCCIO = 1.5V VCCPD = 2.5V While Quartus suggests that the OCT is OK under these conditions, I am waiting for release 12 to re-check it, and will also probably include off chip termination just in case. Although with 68 pairs, this is going to make the layout tricky...

[Altera_Forum]

Got the information today that it is not possible to use a 2.5V LVDS clock input on a 1.5V IO Bank of an ArriaV Chip. Just wanted to let you know... 

 The only strange thing is that Quartus will not bring up an error for this configuration, even when using differential termination on that pin pair.

[Altera_Forum]

Thanks for the update. Was there an explaination of why it cannot be done? Is it because VCCIO must be 2.5V for LVDS? 

 It's a real shame as it means I cannot fit the design in a Cyclone V5CGTFD7D5F3... :(

[Altera_Forum]

Sorry, it's just the information that LVDS inputs are not supported on VCCIO 1.5V banks and a link to the VCCIO / IO Standard matrix.  

Well thats for an Arria chip; I suggest you upen a separate service request for your particular device - maybe that has a different behavior or you get a more detailed description on that.  Our LVDS clock input is now placed on a 2.5V bank and when Quartus 12.0 is release, it hopefully brings the needed bugfix for the engineering samples. I will not investigate more time on that topic.

[Altera_Forum]

Just got this reply from Altera Tec Support saying that I can do this on a Cyclove V: 

 -------------------------------- [Q1]: Assuming that the LVDS input buffers are powered from VCCPD = 2.5V, can I use the LVDS differential inputs if VCCIO is set to 1.5V fro DDR3? [A1]: Referring to the Cyclone V device handbook, it says, “If VCCIO is set to 2.5 V or lower (eg. 1.2, 1.25, 1.35, 1.5, 1.8V), VCCPD must be powered up to 2.5 V. This applies for all the banks containing the VCCPD and VCCIO pins.”   Meaning that if an I/O bank uses a 2.5-V VCCPD (for LVDS), the I/O bank can use different VCCIO voltages provided they are 1.2, 1.25, 1.35, 1.5, 1.8, or 2.5 V.” Thus, for your setup, VCCPD = 2.5V and VCCIO = 1.5V is allowable by Quartus II.   It should [not] be a problem if the design had completed the Quartus compilation without errors message. Quartus will sure give you an error message if the setup is not allowable.   [Q2]: Can I use RD OCT? If not, can I do it with external RD?  [A2]: You are not allowed to use RD OCT, as stated in the device handbook, you can only use RD OCT when you set both the VCCIO and VCCPD to 2.5 V. For your case, VCCPD = 2.5V and VCCIO = 1.5V, you could use external RD. Please refer to the Figure 5–7 which showing the setup of External On-Board Termination.  -------------------------------  supernode: "The only strange thing is that Quartus will not bring up an error for this configuration, even when using differential termination on that pin pair."  Yes, that's strange. I get the same result with Quartus; implying that termination can be used...

[Altera_Forum]

Thank you for letting me know. Like you I also thought of VCCPD to power LVDS input and VCCIO as irrelevant.  

 If you have a little example design that shows the Differential input termination on a 1.5V bank you could add it your service request and have them take a look at it. The fifth generation devices are pretty new so a bug in Quartus may also be possible.   Quartus 12.0 is coming out the next weeks so I would definitley wait for that when before rolling out your board. Although we don't use the LVDS input on a 1.5V bank, please keep on posting updates on this topic when you have new information or tried the clock input setup on your board.

[Altera_Forum]

It's quite obvious, that the Arria V and Cyclone V IO topology is more or less identical. By the present documentation status, one would expect, that the VCCPD powered LVDS input buffers would work in a 1.5 V bank, but differential OCT won't. 

 As long as the support guy doesn't say which part of the Altera device manual is wrong and in which detail, I would consider the possibility that he just doesn't exactly. And the answer must not necessarily be well founded.  Of course lack of information can be a sufficient reason to stay away from the doubted solution.

[Altera_Forum]

Hello! 

Still can't clearly understood, it is possible to use true LVDS transmit and receive (without using external resistors) in the bank with Vccio=1.8v, Vccpd=2.5? According this topic, it's impossible&#1102; But i Create simple project in Quartus 15, compile it without errors.  According Cyclone V Device Handbook update from June 2013 2013.06.17 "Updated the topic about LVDS input RD OCT to remove the require&#8208; ment for setting the VCCIO to 2.5 V. RD OCT now requires only that the VCCPD is 2.5 V."  Somebody tell me who to believe? Quartus or Forum?  Thank in advance!

[Altera_Forum]

Hi KWler, 

In the end we used a bigger device and did not have LVDS mixed with DDR3 so the issue went away... Sorry I can't be of more help.