Cyclone V - Megafunction "ALTIOBUF" Error

[Altera_Forum]

hello, i have some problems using QuartusII megafuction "ALTIOBUF". 

<I'm using Cyclone V(Cyclone V GX Starter Kit) and Quartus 13.1>  I create a new megafunction(ALTIOBUF-select 'As an output buffer','Use output enable port','Enable output buffer dynamic delay chain 1) using "MegaWizard Plug-In Manager".  and compile the design, some error message are occur.  129029 Input port DELAYCTRLIN[4:0 on atom "<name>", which is a cyclonev_delay_chain primitive, is not connected to valid source. 129036 Output port DATAOUT on atom "<name>", which is a cyclonev_delay_chain primitive, is not connected to valid destination.   How can i fix this errors?

[Altera_Forum]

How are you connecting up the buffer - schematically? VHDL? Verilog? Quartus is not happy with the way in which you've instantiated it. 

 Post some code to help us help you  Regards, Alex

[Altera_Forum]

Thanks for your reply. 

 i make the output buffer 'IOBUF_OUT.v' using MegaWizard Plug-in Manager.  Top Level(TEST.v) code and IOBUF_OUT.v code are as follows : module TEST( out_datain, out_io_config_clk, out_io_config_clkena, out_io_config_datain, out_io_config_update, out_oe, out_dataout );  input out_datain; input out_io_config_clk; input out_io_config_clkena; input out_io_config_datain; input out_io_config_update; input out_oe; output out_dataout;  IOBUF_OUT u2 ( .datain(out_datain), .io_config_clk(out_io_config_clk), .io_config_clkena(out_io_config_clkena), .io_config_datain(out_io_config_datain), .io_config_update(out_io_config_update), .oe(out_oe), .dataout(out_dataout)); endmodule  //synthesis_resources = cyclonev_delay_chain 2 cyclonev_io_config 1 cyclonev_io_obuf 1  //synopsys translate_off `timescale 1 ps / 1 ps //synopsys translate_on module IOBUF_OUT_iobuf_out_ll61 (  datain, dataout, io_config_clk, io_config_clkena, io_config_datain, io_config_update, oe) ; input [0:0] datain; output [0:0] dataout; input io_config_clk; input [0:0] io_config_clkena; input io_config_datain; input io_config_update; input [0:0] oe; `ifndef ALTERA_RESERVED_QIS // synopsys translate_off `endif tri0 io_config_clk; tri0 [0:0] io_config_clkena; tri0 io_config_datain; tri0 io_config_update; tri1 [0:0] oe; `ifndef ALTERA_RESERVED_QIS // synopsys translate_on `endif  wire wire_sd1_dataout; wire wire_sd2_dataout; wire [4:0] wire_ioconfiga_outputenabledelaysetting; wire [4:0] wire_ioconfiga_outputregdelaysetting; wire [0:0] wire_obufa_i; wire [0:0] wire_obufa_o; wire [0:0] wire_obufa_oe; wire [0:0] oe_w;  cyclonev_delay_chain sd1 (  .datain(datain[0]), .dataout(wire_sd1_dataout), .delayctrlin({wire_ioconfiga_outputregdelaysetting[4:0]})); cyclonev_delay_chain sd2 (  .datain((~ oe_w[0])), .dataout(wire_sd2_dataout), .delayctrlin({wire_ioconfiga_outputenabledelaysetting[4:0]})); cyclonev_io_config ioconfiga_0 (  .clk(io_config_clk), .datain(io_config_datain), .dataout(), .dutycycledelaysettings(), .ena(io_config_clkena), .outputenabledelaysetting(wire_ioconfiga_outputenabledelaysetting[4:0]), .outputfinedelaysetting1(), .outputfinedelaysetting2(), .outputhalfratebypass(), .outputonlydelaysetting2(), .outputonlyfinedelaysetting2(), .outputregdelaysetting(wire_ioconfiga_outputregdelaysetting[4:0]), .padtoinputregisterdelaysetting(), .padtoinputregisterfinedelaysetting(), .readfifomode(), .readfiforeadclockselect(), .update(io_config_update) // synopsys translate_off  // synopsys translate_on ); cyclonev_io_obuf obufa_0 (  .i(wire_obufa_i[0:0]), .o(wire_obufa_o[0:0]), .obar(), .oe(wire_obufa_oe[0:0]) `ifndef FORMAL_VERIFICATION // synopsys translate_off `endif , .dynamicterminationcontrol(1'b0), .parallelterminationcontrol({16{1'b0}}), .seriesterminationcontrol({16{1'b0}}) `ifndef FORMAL_VERIFICATION // synopsys translate_on `endif // synopsys translate_off , .devoe(1'b1) // synopsys translate_on ); defparam obufa_0.bus_hold = "false", obufa_0.open_drain_output = "false", obufa_0.lpm_type = "cyclonev_io_obuf"; assign wire_obufa_i = {wire_sd1_dataout}, wire_obufa_oe = {(~ wire_sd2_dataout)}; assign dataout = wire_obufa_o, oe_w = oe; endmodule //IOBUF_OUT_iobuf_out_ll61 //VALID FILE   // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module IOBUF_OUT ( datain, io_config_clk, io_config_clkena, io_config_datain, io_config_update, oe, dataout);  input [0:0] datain; input io_config_clk; input [0:0] io_config_clkena; input io_config_datain; input io_config_update; input [0:0] oe; output [0:0] dataout;  wire [0:0] sub_wire0; wire [0:0] dataout = sub_wire0[0:0];  IOBUF_OUT_iobuf_out_ll61 IOBUF_OUT_iobuf_out_ll61_component ( .io_config_clk (io_config_clk), .io_config_clkena (io_config_clkena), .oe (oe), .datain (datain), .io_config_datain (io_config_datain), .io_config_update (io_config_update), .dataout (sub_wire0));  endmodule

[Altera_Forum]

If you wish to use the 'Dynamic Delay Chain' feature of the ALTIOBUF primitive, you need additional constraints in order to enable it to go through fitting. 

 Refer to the User Guide for the ALTIOBUF: i/o buffer (altiobuf) megafunction user guide (http://www.altera.com/literature/ug/ug_altiobuf.pdf). Read through the 'Assignments Necessary For Dynamic Delay Chain Usage' section on page 1-7. This explains the additional constraints you need.  Regards, Alex

[Altera_Forum]

thanks Alex. 

 Error ID 129029 and 129036 occur in 'Analysis & Synthesis', not 'Fitter (Place & Route)'.

[Altera_Forum]

Ah, I see. You need to register both data and oe outside of the primitive - neither can come directly from I/O pins. Refer to figure 1-4 in the same document. It refers to them as 'optional registers' but I don't understand how, in practice, you can get away without them. 

 Regards, Alex

[Altera_Forum]

I have same problems when using "Delay chain" of ALTIOBUF Ipcore with cyclone V. 

 When I create this ip core and install it as top-level entity, I can't complie it although I am success when using this ip core for stratix V.  This is error code when i Ctrl+K:  Error (129029): Input port DELAYCTRLIN[4:0] on atom "iobuf_ipcore:inst|iobuf_ipcore_iobuf_out_cg61:iobuf_ipcore_iobuf_out_cg61_component|sd1", which is a cyclonev_delay_chain primitive, is not connected to a valid source  Info (129004): Input port DELAYCTRLIN[0] of the atom "iobuf_ipcore:inst|iobuf_ipcore_iobuf_out_cg61:iobuf_ipcore_iobuf_out_cg61_component|sd1" is driven by the output port OUTPUTREGDELAYSETTING of the atom "iobuf_ipcore:inst|iobuf_ipcore_iobuf_out_cg61:iobuf_ipcore_iobuf_out_cg61_component|ioconfiga_0", which is a cyclonev_io_config primitive  Info (129004): Input port DELAYCTRLIN[1] of the atom "iobuf_ipcore:inst|iobuf_ipcore_iobuf_out_cg61:iobuf_ipcore_iobuf_out_cg61_component|sd1" is driven by the output port OUTPUTREGDELAYSETTING of the atom "iobuf_ipcore:inst|iobuf_ipcore_iobuf_out_cg61:iobuf_ipcore_iobuf_out_cg61_component|ioconfiga_0", which is a cyclonev_io_config primitive  Info (129004): Input port DELAYCTRLIN[2] of the atom "iobuf_ipcore:inst|iobuf_ipcore_iobuf_out_cg61:iobuf_ipcore_iobuf_out_cg61_component|sd1" is driven by the output port OUTPUTREGDELAYSETTING of the atom "iobuf_ipcore:inst|iobuf_ipcore_iobuf_out_cg61:iobuf_ipcore_iobuf_out_cg61_component|ioconfiga_0", which is a cyclonev_io_config primitive  Info (129004): Input port DELAYCTRLIN[3] of the atom "iobuf_ipcore:inst|iobuf_ipcore_iobuf_out_cg61:iobuf_ipcore_iobuf_out_cg61_component|sd1" is driven by the output port OUTPUTREGDELAYSETTING of the atom "iobuf_ipcore:inst|iobuf_ipcore_iobuf_out_cg61:iobuf_ipcore_iobuf_out_cg61_component|ioconfiga_0", which is a cyclonev_io_config primitive  Info (129004): Input port DELAYCTRLIN[4] of the atom "iobuf_ipcore:inst|iobuf_ipcore_iobuf_out_cg61:iobuf_ipcore_iobuf_out_cg61_component|sd1" is driven by the output port OUTPUTREGDELAYSETTING of the atom "iobuf_ipcore:inst|iobuf_ipcore_iobuf_out_cg61:iobuf_ipcore_iobuf_out_cg61_component|ioconfiga_0", which is a cyclonev_io_config primitive  Info (129030): Output port PADTOINPUTREGISTERDELAYSETTING of a cyclonev_io_config primitive is a valid source for input port DELAYCTRLIN[4:0] on atom "iobuf_ipcore:inst|iobuf_ipcore_iobuf_out_cg61:iobuf_ipcore_iobuf_out_cg61_component|sd1"  Any one help me, plz!!!

[Altera_Forum]

Hi, 

 generally speaking you need to instantiate an IP in your top level file and not set it as the top level file. In VHDL the keyword is components instantiation and I am sure it named similar in Verilog HDL.