Cyclone V PCIe Avalon-ST interface GEN1 x1 test-bench IP - Handling of multiple MSI requests

[Aiswarya]

I am using Cyclone V PCIe Gen1x1 IP core in my project. To verify this design, Altera PCIe Root port BFM is used as the test-bench. While verifying the MSI requests generated from the DUT, it has been observed that few MSI messages are missing at the altpcietb_bfm_driver_chaining.v while polling for MSI. This is observed only when the difference between the MSI requests are about 1 us time period. I am not able to trace back  these MSI signals generated neither from test-bench side (Root port BFM is  protected) nor PCIe express link side.  Because of this, I am not able to find the source of this issue.

I want to check whether there is any limitations for handling the MSI requests (in Altera root port bfm test-bench or PCIe Hard IP) which are generated simultaneously with a time difference of about 1 us. 

Does anyone familiar with this?

[skbeh]

When the Hard IP asserts interrupt, it just means the HIP has created the interrupt message and sent out. It does not mean the message is really out of the TX pin. It also does not mean the host has serviced the interrupt.
When the host side receives the interrupt, it needs to run the interrupt service routine to service the interrupt.
If requesting interrupts too fast, it might get extra interrupts. Next interrupt should only be requested after the previous interrupt being serviced.