Cyclone V PCIe hard IP? Megafunction required??

[Altera_Forum]

Hello, quick question for everyone. I've been looking over the documentation on the Cyclone V PCIe hard IP and not sure if you need to buy a Megafunction to implement a PCIe link on the Cyclone V? The documentation states, "The PCIe hard IP consists of the MAC, data link, and transaction layers". What exactly is "hard IP"? I found the following in the documentation, "The Cyclone® V PCIe hard IP operates independently from the core logic" what is this and how is it different than lets say implement a PCIe link on a Stratix IV fpga?

[Altera_Forum]

Hardened IP is a block of logic in the FPGA that has fixed functionality - e.g. PCI Express. Core logic is general purpose logic configurable to your needs. 

 See the "pci express protocol (https://www.altera.com/products/intellectual-property/ip/interface-protocols/m-pci-express-protocol.html#device-support---hardened-ip-blocks--generation---link-width-configurations---feature-support)" IP page for a little more info.  Cheers, Alex

[Altera_Forum]

Alex, 

 Hello, thanks for responding to my post. I was beginning to feel that no one would respond. So I will need to purchase a PCIe megafunction, rats! They are not cheap.   So here's another question. If Core Logic is able to implement a PCIe link whey would Altera put a Hardened IP block?   Joe

[Altera_Forum]

Joe - 

 You already paid for the hard IP core - it's built into the silicon. No need to buy a soft core. You just have to learn out how to configure the core and instantiate it in your design. The hard IP core should be listed in the IP catalog. Pull it up and configure it for what you need (root port or end point, speed, lanes, interface, etc). The preferred way to do this is with Qsys, but you don't have to do it that way. There's a bit of a learning curve with the tools and methods. It's usually easiest to start with a reference design. This link might help you:  http://www.alterawiki.com/wiki/cyclone_v_pcie_avalon-mm_multifunction    Bob

[Altera_Forum]

Bob, 

 Hello, and thank you, thank you for responding to my post. I'm so relieved to know that I don't need to purchase a Megafunction like my co-workers did when they implemented a PCIe link on their Stratix 4. I'm going to look into this Hard IP as you suggested.  Have a splendid day!

[Altera_Forum]

Bob, 

 Hi, I passed this information onto my co-worker and he gave me a few more details of his design. I said that he purchased a Third party PCIe Megafunction that implemented only the DMA Engine and use Altera's free PCI megafunction. He said if the Hard IP can implement something similar that you give the function a go and it will run independently reading the source memory and transmitting it over the PCIe link then that is great. I printed out the V-Series Avalon-MM DMA Interface for PCIe Solutions and will look if the Hard IP can implement a DMA engine. Do you have any comments or suggestions?  Thanks, Joe

[Altera_Forum]

Hi Joe - 

 I have not used PCIe in a Cyclone V. So I can't comment specifically on PCIe DMA solutions in Cyclone V. But Altera does have free (with a Quartus license) modular scatter-gather DMA cores (mSGDMA). As I said before, I highly encourage you to leverage any available reference designs applicable to what you're doing. And if you don't have a Cyclone V dev kit get one so you can run the reference designs.  Here's a PCIe end point design that includes the mSGDMAs and targets Cyclone V:  http://www.alterawiki.com/wiki/pci_express_in_qsys_example_designs#hardware  Hope this helps!  Bob

[Altera_Forum]

I recommend you get a cyclone v gt fpga development kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-gt.html), or at the very least download the 'Kit Installation' (link at the bottom of the page) and explore the examples. 

 This kit uses the Cyclone V GT's PCI Express hard IP block - as well as a hard memory controller. Everything you need to explore the PCIe hard block and DMA transfers - either to/from host or local memory.  Further reading: ip compiler for pci express user guide (https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahukewjr9bza3thmahxkfrokhbyddfaqfggcmaa&url=https%3a%2f%2fwww.altera.com%2fliterature%2fug%2fug_pci_express.pdf&usg=afqjcnh70svgqfxfxgufql7dgu2ix29uxa&bvm=bv.121658157,d.bgg) and the cyclone v avalon-st interface for pcie solutions user guide (https://www.altera.com/literature/ug/ug_c5_pcie_avst.pdf).  I think (hope) between these docs and reference designs you'll be able to see a solution you're happy with.  Cheers, Alex