DE0 nano Cycl.V: SDRAM parameters for Qsys

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

DE0 nano Cycl.V: SDRAM parameters for Qsys

851 Views

Hi everyone!

At first: I am new to FPGA/VHDL, but I am in a project at the University, where we are trying to learn the basics of FPGA-programming "by doing".

For our Project we now want to use the SDRAM as a fifo-memory for the VGA-data. I therefore watched a video on youtube (https://www.youtube.com/watch?v=euw0illtehm), which is really really good! The only problem is, that it is for the DE1 nano - not the DE0 nano.

So my problem is now: where can I find the coorect settings for the Qsys-SDRAM-Controller? Like Rows, Columns, Chip Select, Banks, Timings etc? I know that it should be somewhere in the Datasheet but i realy cannot imagine which value is which (especially rows and columns).

Cheers and thank you very much in advance!!!

Link Copied

0 Replies

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.