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Valued Contributor III
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DE0 nano Cycl.V: SDRAM parameters for Qsys

Hi everyone! 

At first: I am new to FPGA/VHDL, but I am in a project at the University, where we are trying to learn the basics of FPGA-programming "by doing". 

For our Project we now want to use the SDRAM as a fifo-memory for the VGA-data. I therefore watched a video on youtube (https://www.youtube.com/watch?v=euw0illtehm), which is really really good! The only problem is, that it is for the DE1 nano - not the DE0 nano. 

 

So my problem is now: where can I find the coorect settings for the Qsys-SDRAM-Controller? Like Rows, Columns, Chip Select, Banks, Timings etc? I know that it should be somewhere in the Datasheet but i realy cannot imagine which value is which (especially rows and columns). 

 

Cheers and thank you very much in advance!!!
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