Cyclone V PLLs don't lock

[Altera_Forum]

Hello, 

we are developing a board with 2 Cyclone V FPGA  5CEBA4F23C7N 5CGXBC4C6F27C7N  at the moment we have 3 copies of the board produced in december and 3 copies produced in october.  None of the board have all PLLs working. The number of PLLs that lock vary from board to board and moreover PLLs that lock on one board don't lock on another one. We are this issues on both FPGA.  Originally the power supply was provided by switching regulators. The measured power noise was in the limit of +-5% of the 2.5V rail. Now we disconnected all switching power supply and replaced with linear power supply but nothing change.  One of the four PLLs of the 5CEBA4F23C7N starts to lock if we set the bandwidth to high.  The clock is generated by a 50MHz 3.3v oscillator 50R terminated close to the FPGA PIN.  The clocks generated by the locked PLLs have a stong jietter.  We are looking for a solution. We can not redesign the board without understanding where is the problem  Thanks

[Altera_Forum]

https://www.altera.com/support/support-resources/operation-and-testing/pll-and-clock-management/pll-loss-lock.html

[Altera_Forum]

just in case, please check if RREF resister is connected.

[Altera_Forum]

Yes, it was the RREF missing. Thanks very much!!!! 

 Andrea