Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Cyclone V Passive Serial configuration failing after many bits.

ESaiv
New Contributor I
626 Views

Hello. I am attempting to configure my Cyclone V SoC FPGA using passive serial (PS) configuration on a custom PCB. Sometimes, my configuration fails at the 1st bit; other times, it fails after something like 49000 bits. 

The actual error message is below - the exact number of bits varies from 1 to about 49000, so far:

Error (209010): Device did not accept configuration data (after 16384 bits sent).

Is there a best place to look for why a configuration would fail halfway through? I slowed my USB-Blaster II cable down to the slowest possible of 10 kHz. 

For extra information, so far, the most common error point is 8192 bits.

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5 Replies
YuanLi_S_Intel
Employee
596 Views

May i know which quartus version you are using? Can you try with latest version?


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ESaiv
New Contributor I
588 Views

Hi. I am using Quartus Standard 20.1.

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YuanLi_S_Intel
Employee
553 Views

The error might be caused by the following issue. Can you please check?


  • Incorrect device selected
  • User start up clock selected but no running clock connected to CLK_USR pin
  • Communications cables not securely connected
  • No power to target system


ACTION: Make sure all cables are securely connected, select a different device, check the power on the target system.Make sure you have connected a start-up clock for initialization of the CLKUSR pin, or specify that the device not use a user-supplied clock on the CLKUSR pin for initialization.


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ESaiv
New Contributor I
543 Views

Hello, 

Thanks for the response. I ensured each of those things were done. I fixed my issue by re-floating a few pull-up resistors on important pins such as nSTATUS, nCONFIG, etc. All works well now.

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YuanLi_S_Intel
Employee
524 Views

I am glad it works now. Hopefully it will help the community who have this issue. Thank You.


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