In my design I am using different power supplies and LDOs for the respective power rails of the cyclone V FPGA. My question is this, if I disable the VCCIO power rail, what would happen to the FPGA?
When I did that in my design, the output of the LDO, which is typically 1.8V (that goes to the VCCIO) still measures 1.4V, even though the enable pin for the LDO is low. Is it possible that this 1.4V is coming from FPGA itself, as the power rails (VCore, Vccpgm, etc) are still energized. Please advise.
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