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Honored Contributor I

Cyclone V SE Power management

Hello everyone, 

I plan to use a SoC Cyclone V in replacement of a ARM9 + Cyclone II solution, and it will be powered by a battery. 


I used the power plan estimator for the consumption, and I found for the 5CSEBA2 typical consumption of 1,15W, at maximum frequency (925 MHz) for the HPS. 


Is there is a kind of power management system integrated inside the Cyclone V SE ? 

To reduce the clock frequency, to enter in idle mode ? 


Is the static power displayed in the power plan estimator the consumption in idle state ? 



I hope you can enlight me, 

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Honored Contributor I



The power estimator is able to display static power. For the HPS, you can reduce the freq during compilation (it will change the divider of PLL). Unfortunately, I don't see any power management system inside the HPS (for example, to automatically change PLL divider). There is a software example that will put the MPU to IDLE mode though: 


(search for "Power Optimization" under SoC design examples 


Another way you can reduce power is to power down the FPGA when unused. Of course this means the regulator control will have to be done by HPS. If this is relevant to you, I've seen an example project that does that.