I'm trying to access CAN0 in a Cyclone V SOC from a NIOS in the FPGA. I've added an address extender to the NIOS data bus, and an Avalon-MM Pipeline Bridge between the extender master port and the HPS f2h_axi_slave. My problem is that no combination of parameters
I've tried for the the extender and the bridge work. Platform Designer rejects the values that make the most sense to me. What it accept does not work.
The description of the extender in Platfor Designer System Design Components does not help (some of the text is just wrong). The online video for the extender is an incomprehensible rehash of the document.
Does anyone have an idea how to get this to work?
I found a solution. I don't have time to explain fully. The key is setting the appropriate bit(s) in the l4sp register (part of the l3regs group) that allow the f2h_axi_bridge access to the desired HPS device(s), such as CAN0. I cannot see any way to have Platform Designer/Quartus set the l4sp register as part preloader or FPGA image. The ARM processor has to do it (in Linux open /dev/mem and use mmap() to write the register).