Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20889 Discussions

Cyclone V SOC design upgrade from Quartus 18.1 to 20.1

MStof1
Beginner
1,998 Views

I have a Cyclone V SOC FPGA design that compiles fine in Quartus version 18.1.

However, when I upgrade the design to Quartus version 20.1, adding WSL, the design upgrades, indicating no errors, but fails to compile.  Generate HDL in Platform Designer generates without errors (before the compile).

An example error from Analysis & Synthesis:  "Error (10481): VHDL Use Clause error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(7): design library "altera_sld" does not contain primary unit "sld_hub_pack". Verify that the primary unit exists in the library and has been successfully compiled."

These same results have occurred using Quartus 20.1 Lite and also using Quartus 20.1 Standard with an evaluation license.

How do I get this to compile?  I'm getting very frustrated.

0 Kudos
1 Solution
Nurina
Employee
1,948 Views

Hi,


I think this has something to do with your file path. Because now that your project is compiled on a shared drive, Quartus cannot find the "sld_hub_pack" file since your Quartus software is installed to your PC.


You should map a network drive to the shared drive. This way the shared drive is mapped on your PC drive and Quartus is now able to find the file.


Here are steps for you to do so: https://support.microsoft.com/en-us/windows/map-a-network-drive-in-windows-10-29ce55d1-34e3-a7e2-4801-131475f9557d


Regards,

Nurina


View solution in original post

0 Kudos
6 Replies
Nurina
Employee
1,981 Views

Hi,


Can you post the full error log? Is your project compiled on your local drive on PC?


Regards,

Nurina


0 Kudos
MStof1
Beginner
1,975 Views

The Quartus tool is installed on the PC's local drive.  The project is not.  It needed to be on a drive that is accessible from other PCs.

The full error log:

Warning (12019): Can't analyze file -- file //albmain/share/EngLab/StofferM/SBR_1_v18p1_good_compile_restored_in_v20p1/sld_hub.vhd is missing
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld51cb7f85/alt_sld_fab.v
Info (12023): Found entity 1: alt_sld_fab
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld51cb7f85/submodules/alt_sld_fab_alt_sld_fab.v
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld51cb7f85/submodules/alt_sld_fab_alt_sld_fab_ident.sv
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_ident
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld51cb7f85/submodules/alt_sld_fab_alt_sld_fab_presplit.sv
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_presplit
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/sld51cb7f85/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd
Info (12022): Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sld51cb7f85/submodules/alt_sld_fab_alt_sld_fab_splitter.sv
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_splitter
Error (10481): VHDL Use Clause error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(7): design library "altera_sld" does not contain primary unit "sld_hub_pack". Verify that the primary unit exists in the library and has been successfully compiled.
Error (10800): VHDL error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(7): selected name in use clause is not an expanded name
Error (10481): VHDL Use Clause error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(8): design library "altera_sld" does not contain primary unit "sld_jtag_hub_pack". Verify that the primary unit exists in the library and has been successfully compiled.
Error (10800): VHDL error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(8): selected name in use clause is not an expanded name
Error (10481): VHDL Use Clause error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(9): design library "altera_sld" does not contain primary unit "jtag_pack". Verify that the primary unit exists in the library and has been successfully compiled.
Error (10800): VHDL error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(9): selected name in use clause is not an expanded name
Warning (12241): 40 hierarchies have connectivity warnings - see the Connectivity Checks report folder
Info (144001): Generated suppressed messages file //albmain/share/EngLab/StofferM/SBR_1_v18p1_good_compile_restored_in_v20p1/output_files/SBR_1.map.smsg
Error: Quartus Prime Analysis & Synthesis was unsuccessful. 6 errors, 99 warnings
Error: Peak virtual memory: 5301 megabytes
Error: Processing ended: Thu May 20 10:45:46 2021
Error: Elapsed time: 00:05:49
Error: Total CPU time (on all processors): 00:05:09

 

Also see warnings like one shown below, which has never been the case on any other project (I wonder if the Quartus install was done correctly since I can't do it - has to be done by our IT department):

Warning (12125): Using design file db/altsyncram_7nn1.tdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info (12023): Found entity 1: altsyncram_7nn1

0 Kudos
MStof1
Beginner
1,967 Views

I tried copying the project to the local C: drive of the PC being used.  Now the project compiles! 

 

This is something that changed from version 18.1 to 20.1!  I was using the project in the same folder with version 18.1 with no problems.

This is a problem, since others need access to this project.

0 Kudos
Nurina
Employee
1,949 Views

Hi,


I think this has something to do with your file path. Because now that your project is compiled on a shared drive, Quartus cannot find the "sld_hub_pack" file since your Quartus software is installed to your PC.


You should map a network drive to the shared drive. This way the shared drive is mapped on your PC drive and Quartus is now able to find the file.


Here are steps for you to do so: https://support.microsoft.com/en-us/windows/map-a-network-drive-in-windows-10-29ce55d1-34e3-a7e2-4801-131475f9557d


Regards,

Nurina


0 Kudos
MStof1
Beginner
1,930 Views

I had thought the drive was mapped, but that was on another PC.  After I mapped the drive, it compiles.  Thank you.

 

I still don't quite understand since the full path name was there and there were no spaces anywhere in the path.

0 Kudos
Nurina
Employee
1,920 Views

Hi,

 

I'm guessing Quartus can only find files in a local PC drive (C: or F: etc.). This problem has been reported to engineering too.

 

With that, I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

 

Regards,
Nurina

PS: If you find any comment from the community or Intel Support to be helpful, feel free to give Kudos.

0 Kudos
Reply