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Beginner
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Cyclone V SoC: When routing HPS CAN0 or CAN1 pins to FPGA receive direction isn't working

I'm using Quartus Prime Lite 16.1.

I am programming a Cyclone V Soc on a SocKit / DeNano board.

I am accessing the CAN controllers with bare metal code from the second ARM core.

 

With Qsys I selected

 

CAN0 pin = FPGA

CAN0 mode = Full

CAN1 pin = FPGA

CAN1 mode = Full

 

The soc_system then has 4 addtional signals

 

     hps_0_can0_rxd : in   std_logic := 'X'; -- rxd

     hps_0_can0_txd : out  std_logic;         -- txd

     hps_0_can1_rxd : in   std_logic := 'X'; -- rxd

     hps_0_can1_txd : out  std_logic          -- txd

 

I 'connected' these signals to the appropriate I/O pins.

 

I can set the txd pins via test regsiter ctr->Tx and, using loopback mode I can send data.

 

Receive direction isn't working at all.

I can't even 'see' static levels at the input pin with test register ctr->Rx. (Loopback mode off!)

 

I connected the Rx signals to an addtional output pin and I can see the level is recognized in the FPFA.

It's just not transferred to the HPS.

 

What did I possibly do wrong?

 

What can I check?

 

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3 Replies
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Employee
9 Views

Hello sir,

So I would check the following items:

1- make sure the CAN is enabled in device tree.

2- Signal tap the routed signals in FPGA. You can send them to me for further investigation.

3- Is there any linux image working?

 

Thanks

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Beginner
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Hello!

 

1

CAN is NOT enabled in device tree because I'm NOT using Linux

 

2

I will signal TAP, but I guess that will only tell me what I already know:

transmit is working, receive signal is correct in FPGA but does not reach HPS.

 

3

There is a Linux working on core 0, but it has no CAN driver and no CAN in device tree.

CAN is accessed by core 1 with bare metal software, only.

 

Joachim

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Highlighted
Employee
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Hello Joachim,

the signaltap will help us to understand where is the failing point.

 

Thanks

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