Cyclone V SoC custom board preloader boot sdram test issue

[BrianSune_Froum]

Dear Intel FAE and ALL,

This is Brian and having issue on maximum 2GB DDR3 boot sanity test.

There is a warning like these:

"SDRAM: Running EMIF Diagnostic Test ...Iteration 1734:, expect 0x20a69210 from address 0x20a69213, read 0x20a69210 insteadFailed"

But w/o the SDRAM test on preloader, the system can boot into distro and passed memtester.

Do the preloader have any bug on the memory size of the SDRAM?

It do show a 2048M size message.

memtester log:

```

brian@brian:~$ sudo memtester 1900M
memtester version 4.3.0 (32-bit)
Copyright (C) 2001-2012 Charles Cazabon.
Licensed under the GNU General Public License version 2 (only).

pagesize is 4096
pagesizemask is 0xfffff000
want 1900MB (1992294400 bytes)
got 1900MB (1992294400 bytes), trying mlock ...locked.
Loop 1:
Stuck Address : ok
Random Value : ok
Compare XOR : ok
Compare SUB : ok
Compare MUL : ok
Compare DIV : ok
Compare OR : ok
Compare AND : ok
Sequential Increment: ok
Solid Bits : ok
Block Sequential : ok
Checkerboard : ok
Bit Spread : ok
Bit Flip : ok
Walking Ones : ok
Walking Zeroes : ok
8-bit Writes : ok
16-bit Writes : ok

Loop 2:
Stuck Address : setting 3^C

```

[JingyangTeh_Altera]

Hi

Could you share what uboot version that you are using?

There is no known issue for the recommended uboot version socfpga_v2024.07.

Regards

Jingyang, Teh

[BrianSune_Froum]

@JingyangTeh_Altera 

The work stations are in Quartus 18.1.

So the uboot is generated via make uboot from bsp-editor MakFile.

Do you mean even the EDA is 18.1 the ARM development can still updated to latest?

I am not too sure on uboot, as for the kernel it is using most latest 6.12.11 dirty.

The DDR3 2GByte is fully tested on distro even ran the frame-buffer w/o any issue.

This is why it is very puzzling why larger than 1GByte will have such issue.

Opps,

I think you had misunderstand the issue point correct me if I misunderstand.

The issue is happened on "preloader" dram check not uboot phase?

The check is ran via the spl.c on the sdram check function if I understood it right.

[JingyangTeh_Altera]

Hi

Apologize for the late reply.

For the new flow the SPL s no longer generated from the bsp-editor.

The SPL version is tied together with the u-boot version.

It is still separate from the uboot. ( https://github.com/altera-fpga/u-boot-socfpga/blob/socfpga_v2024.07/arch/arm/mach-socfpga/spl_gen5.c)

In the latest spl code, there is no longer sdram diagnostic test.

New flow:

https://altera-fpga.github.io/rel-25.1.1/embedded-designs/cyclone-v/sx/soc/boot-examples/ug-linux-boot-cve-soc/#the-new-flow

Regards

Jingyang, Teh

[BrianSune_Froum]

@JingyangTeh_Altera 

Allow me, based on my ultra lite knowledge on U-Boot and SPL.

The DDR_SI test actually can be transferred from old U-Boot to latest mainstream Das U-Boot (Altera U-Boot).

According to Siemens patches I do see s.t. very similar.

This is just feature that Altera plan to do so or not.

Apart from U-Boot version I cannot see such test is very complex compared to old 2013 trunk.

Meanwhile, the U-Boot itself from mainstream already included calibration of SDRAM, but had not study deep on such test.