Cyclone V SoC interrupt IDs

[SGlow]

I'm working on a bare metal application on a Cyclone V Soc.  I'm making progress, but the documentation for this device seems a bit scattered. 

One thing I'm having trouble finding is the interrupt IDs for the GIC.  I can't seem to find this in any of the available pdf files or the online HPS register maps.  Does anyone know where this might be documented?

Thanks,

Steve

[aikeu]

Hi SGlow,

You can check with this Cyclone V HPS Technical Reference Manual document:

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/hard-processor-system-technical-reference.html

There are information regarding GIC interrupt Controller which may help to answer your question.

Thanks.

Regards,

Aik Eu

[SGlow]

Hi Aik Eu,

Thank you for the response.  I've been using that document as one of my primary sources of information on the HPS system bit it only makes a few passing references to the GIC.  To actually program the GIC I needed to refer to the ARM ARM Generic Interrupt Controller architecture spec.

I now have the GIC working, but need to know the interrupt IDs associated with the various peripherals of the HPS.  For example, the HPS includes two UART modules which are documented in the manual that you linked.  Each of those UARTs outputs an interrupt signal that goes to the GIC.  In order to program the GIC to acknowledge those interrupts I need to know the interrupt IDs for each of them but so far I can't find that documented anywhere.

This seems like a pretty significant omission in the documentation for this part so I'm hoping that I've just missed a table somewhere, but I've spent hours searching for it with no success so far.  I would appreciate it if someone would point me in the right direction.

Thanks,

Steve

[Tru]

It is in the same document as given above, but you need to open up the chapter 10 tree - yeah very strange tree document system they have.  Anyway, here you go:

https://www.intel.com/content/www/us/en/docs/programmable/683126/21-2/gic-interrupt-map-for-the-soc-hps.html

[aikeu]

Hi SGlow,

If it is related to the device tree interrupt value:

Example:

For HPS UART0 it is 162

For HPS UART1 it is 163

Referring to the GIC Interrupt map:

For HPS UART0 it is 194, so minus 32 will be 162

For HPS UART1 it is 195, so minus 32 will be 163

You may use the below two documents for your reference:

https://developer.arm.com/documentation/ihi0048/latest/

http://ecse324.ece.mcgill.ca/_downloads/eb3bd46aeaebdd7c592e61dbc13dc1d3/Using_GIC.pdf

Thanks.

Regards,

Aik Eu

[SGlow · Accepted solution]

Yes, thank you Aik Eu and Tru, I see the info now.

It turns out that my problem was an incomplete pdf version of the manual.  The pdf manual that you get when you press the download button on the on-line manual page includes this information as chapter 10.  The manual I've been working from has the same name (cv_5v4) and same date (2021.07.08) but doesn't include this chapter.  On the manual I've been using chapter 10 is the CoreSight debug chapter which is chapter 11 in the newer manual.

Very strange, I thought I had gotten my pdf through the same download link a few weeks ago but perhaps I found it elsewhere.

Anyway, I have the info I need now so thank you both very much!

- Steve

[aikeu]

Hi SGlow,

Good to know that your issue has been resolved. I will close this thread for now.

Thanks.

Regards,

Aik Eu