Cyclone V configuration bank I/O voltage

[EdJ]

I have virtually the same question asked 7 years ago in this forum. (https://community.intel.com/t5/Intel-Quartus-Prime-Software/Configuration-I-O-voltage/m-p/140486#M32761). 

I don't think it was answered with complete certainty.

I am using LVDS inputs in bank 3A of the Cyclone V E (5CEBA5F23C7).  This is the I/O bank containing the configuration pins.  I want to use the ASx4 configuration scheme (EPCQ128) and be able to program the config device through JTAG using the Serial Flash Loader.  The circuit is shown in Figure 7-14 of the Cyclone V Device Handbook, Volume 1 (CV-5V2).  It seems straightforward based on the documentation in Chapter 7 of CV-5V2 :
VCCPGM
"The configuration input buffers do not have to share power lines with the regular I/O buffers in Cyclone V devices.
The operating voltage for the configuration input pin is independent of the I/O banks power supply, VCCIO, during configuration. Therefore , Cyclone V devices do not require configuration voltage constraints on VCCIO ."

We are using VCCPGM = +3.3V which is required for the ASx4 configuration scheme, while VCCIO3A = +2.5V (required by LVDS).
The JTAG power and pull up should be VCCPD3A = VCCIO3A = +2.5V.  MSEL 0,1,4 tied to VCCPGM (+3.3V), MSEL 2,3 tied to GND. 

However, some uncertainty sets in when I look at the Device and Pin options in Quartus.  I set the proper parameters (ASx4, EPCQ128A, 3.3V config device I/O voltage).  There is a box "Force VCCIO to be compatible with configuration I/O voltage".  When I don't check it, there are no errors.  When checked, errors concerning illegal I/O voltages pop up.  This is clear since the LVDS inputs in the bank require VCCIO = 2.5V.  In light of the flexibility stated in the documentation, when would someone want/need to check that box?  (I'm NOT utilizing the configuration pins as I/O after configuration is done.)

Thanks if anyone can shed some light on this and remove any lingering doubts in my mind.  Let me know if there are any problems hiding here.

Ed

[AminT_Intel]

Hello,

I am sorry you still have the same problem after 7 years. May I know what error did you receive when that box is checked?

Force VCCIO voltage to be compatible with configuration I/O voltage—Forces the VCCIO voltage of the configuration pins to be the same as the configuration device I/O voltage. If you turn off this option, the VCCIO voltage of the configuration pins may vary depending on the I/O standards used in the I/O banks containing the configuration pins. This option is available for supported device families.

Thank you.

[EdJ]

Sorry, it was somebody else that asked the question 7 years ago. I located it when I searched the forum before I posted. The reason for the option in Quartus to force I/O voltages in the bank to be consistent with VCCPGM was not made clear in the responses to that question. That question as well as mine referred to the Cyclone V series. After posting I realized that other chips supported by Quartus may require that the I/O in the config bank must have the same voltage as the programming voltage, so that is why the box option is there.
While I have your attention, could you confirm that my scheme and voltage choices (JTAG voltage, JTAG pull-up voltage, config pin pull-up voltage, I/O bank 3A voltage) described in my 1st post are correct for ASx4, with config device programming via the Serial Flash Loader? Thanks a lot.
Ed

[AminT_Intel]

Hello,

I think your scheme and voltage choice looks good so far. You can refer to Pin Connection Guidelines for more details on power supply: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-v/pcg-01014.pdf

Thank you.

[AminT_Intel]

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