Cyclone V custom board VCCIO puzzling behavior

[BrianSune_Froum]

Dear Intel and all,

I am working on Cyclone V soc 5CSEBA5U19C8N.
There is a very puzzling VCCIO behavior.
According to "Cyclone® V Device Family Pin Connection Guidelines
PCG-01014-3.2".

Any 3.0 below VCCIO must use a VCCPD with 2.5V.
I am supplying VCCIO of bank 3B+4A with VCCPD 2.5V and the VCCIO is using 1.2V.
However when measuring the VCCIO rail the voltage raised to almost 1.5V.

Before the FPGA chip is applied the voltage rail is able to measure clean 1.2V which eliminates the DCDC issue.

This is very puzzling, please FAE or Intel employee support.

Thank you

[BrianSune_Froum]

@Farabi 

Please do investigate with internal and provide solution and possible causes on such behavior.

This ensure other designer and user should know what VCCPD and VCCIO could be supported.

Bests,

Brian

[Farabi]

Hello,

I have filed investigation request to engineering: 15018404392

This will take some time but engineering will take a look into this.

regards,

Farabi

[BrianSune_Froum]

@Farabi 

This will help to check how much leakage and possible hazard.

BTW the compile settings make unused IO to output still introduce such problem.

The previous responses are included as much experiment data as possible.