I'm trying to reproduce the Altera Example design "Cyclone V Native PHY with external fPLL design example" on my custom board.
The only change I made to the project is the fPLL source clock period.
Unfortunately, I have some problem with the clock management.
In particular, I in my custom board the PHY signal "rx_is_lockedtoref" is not stable to '1'.
What can be the problem? My fPLL clock source is a 50MHz oscillator, this clock could be with a too high jitter?
You may need to check whether your fPLL is able to lock , and the reference clock is stable. If you are using lock to data mode, the lock to ref is not necessary to stable to 1 all the time, but you need to check the lockedtodata signal.
Regards -SK Lim (Intel)