Cyclone reset/POR

[Altera_Forum]

Hi, 

I'm using the cyclone EP1C6 device. Just to make sure - which pin can be used as the reset state monitoring pin, meaning that in the VHDL code I can write (for example): if (reset = '0') then... Which pin can be assigned as the reset pin? I understand that the CONF_DONE pin can do that?  Thanks in advance

[Altera_Forum]

CONF_DONE can't be read in user code. And you don't need to. 

 You can refer to the POR by setting initial values for signals. In Verilog, they are set from an initial block. You can also rely on the fact, that all Verilog registers respectively VHDL signals are initialized to zero unless you set the global "power-up don't care" synthesis option. So for synthesis, you would only need to specify non-zero initial content of registers. In ModelSim functional simulation howver, all registers have an unknown 'U' state. If the design is intended for simulation, you should also explicitely include the zero initialization.

[Altera_Forum]

Hi FvM, 

thanks for the reply. I'm not a VHDL expert but when I write the code I usually write something like: if reset = '0' then  ...  ...  ... elsif rising_edge(clk) then  ...  ...  ...  If I understand correctly you're saying that there is no need for the first "if" so I should initialize all the values in the object declaration section and in the code itself just start from the "if rising_edge(clk)..." part?

[Altera_Forum]

--- Quote Start ---  I'm not a VHDL expert   --- Quote End ---   It's not a VHDL problem. It's about imagining how the FPGA hardware works.  The reset case will be needed, if you have a different reset source than POR, e.g. a reset input that's resetting all or some registers without reloading the configuration. If you don't have it, you don't need the reset case.  Another option is to have an internal reset generator in your design, that is controlling the global reset signal. The the reset case would be needed, too. It's meaningful, if you require the POR reset to be released synchronously but don't have a hardware reset input.  Generally, it's no harm to include the reset case and a global reset signal with your design and wire it to a constant in the top entity. Then you're prepared for later extensions.

[Altera_Forum]

I do have an external reset option on the DEV_CLRN pin. So how can I monitor the reset state in the code? Which external pin can be used for that? Or is there a special internal function for that?

[Altera_Forum]

You can either enable the DEV_CLRN pin as global reset, then it has the same effect as a POR. As said above, it would restore the initial values set in your code, trigger initial blocks etc. 

 Or you disable the gobal function of this pin and connect it to an explicite reset signal defined in user code, driving the said reset case and asynchronous reset inputs of Altera Megafunctions if needed.