Cyclone10LP SEU CRC error implementation (part 2)

[UF1]

Dear support team,

I open a new post as the first has been closed without an answer, only references to already read documentation .

We have enabled the CRC_ERROR pin and we want to instantiate the block cyclone10lp_crcblock in order to retrieve the CRC calculated during configuration.

The cyclone10lp_crcblock is instantiated in a dedicated IP (attached with this message) where the CRC is output after 10s during 32 clocks.

When observed with signaltap there is no data output from the cyclone10lp_crcblock, could you help us to solve this issue ?

Below is the VHDL code used to output the CRC code :

//----- Instantiation and configuration -------------------------------------------------------

uut_cyclone10lp_crcblock : cyclone10lp_crcblock
generic map
(
oscillator_divider => 8 ,
lpm_type => "cyclone10lp_crcblock"

)
Port map
(
clk => s_clk_crcblock ,
shiftnld => s_shiftnld ,
ldsrc=> s_ldsrc ,
crcerror => s_crcerror ,
regout => s_regout
);

s_shiftnld <= '0';
s_ldsrc <= '0';

s_clk_crcblock <= i_clk when s_output_crc='1' else '0';

o_regout <= s_regout;

o_error_pin <= s_crcerror;

//----- Process to output data -------------------------------------------------------

pro_get_crc32: process(i_clk)
begin

if i_rst = '0' then

sv_cnt <= (others=>'0');
sv_crc32 <= (others=>'0');
s_output_crc <= '0';

elsif rising_edge(i_clk) then

-- Wait 10 s @ 60MHz then output register : 600000000
if unsigned(sv_cnt) = 600000000 then
s_output_crc <= '1';
sv_cnt <= std_logic_vector(unsigned(sv_cnt) + 1);

-- Stop after 32 clocks 600000032
elsif unsigned(sv_cnt) = 600000032 then
s_output_crc <= '0';
sv_cnt <= std_logic_vector(unsigned(sv_cnt) + 1);

-- Stop counter 33 clocks 600000033
elsif unsigned(sv_cnt) = 600000033 then

-- Count after reset
else
sv_cnt <= std_logic_vector(unsigned(sv_cnt) + 1);
end if;

if s_output_crc = '1' then

sv_crc32 <= sv_crc32(sv_crc32'length-2 downto 0) & s_regout;

end if;

end if;
end process;

//---------------------------------------------------------------------------------------------

Regards,

GB

[Farabi]

Hello,

This is to let you know I have been assigned to this case.

I am checking your request and get back to you as soon as possible.

regards,

Farabi

[Farabi]

Hello,

Is your design following this guide? link : https://www.intel.com/content/www/us/en/docs/programmable/683777/current/accessing-error-detection-block-through.html

Can you share .qar file so we can try at our setup.

regards,

Farabi

[UF1]

Hello Farabi,

I can't share you the whole project but attached is the VHDL file of IP instantiated at the top. I use signaltap to visualize the output of the of cyclone10lp_crcblock.

> Is your design following this guide? link : https://www.intel.com/content/www/us/en/docs/programmable/683777/current/accessing-error-detection-block-through.html

Yes, I followed this guide and read the documentation of the handbook (ID 683777) chapter 7 "Seu mitigation in Intel Cyclone10 LP Devices". We use the device Cyclone 10 LP 10CL120YF484I7G.

Thanks for your support,

GB

2.15.0.0

[UF1]

Farabi,

Do you have an example project implementing the CRC read feature we can start with ?

Regards,

GB

2.15.0.0

[Farabi]

Hello,

I am sorry for late reply. For ref design, can you access this link ?

CRC ref design link C10LP : https://www.intel.com/content/www/us/en/design-example/714548/intel-cyclone-10-lp-fpga-nios-ii-processor-custom-instruction-for-intel-cyclone-10-fpga-design-example.html

I can forward the design to you if you dont have access to this link.

regards,

Farabi

[Farabi]

Hello,

Do you have further request?

regards,

Farabi

[UF1]

Farabi,

It doesn't answer to the initial question, the point is to instantiate the primitive cyclone10lp_crcblock of a Cyclone10LP device in order to get the calculated CRC32 of the RAM. The link corresponds to a custom CRC implementation on a Nios.

This issue has been opened from 3 months and has been published over 2 different posts because your quality procedure close a ticket even when no  answer is provided.

Please make your organization aware that the customer quality has really decreased compared with the original Altera company. At that time, even a small company had a direct contact with a support engineer from Altera or a distributor. Now, everything is tracked but there is no more answer. As a reminder, we are not asking for a very specific rocket-science question but only how to use a feature of your device.

You and your colleagues are not responsible of this blocking point only is your organization because of political choices.

Regards,

GB

2.15.0.0

[Farabi]

Hello GB,

I am sorry my answer does not answer your question.

To have a better communication, can we have a call?

I will send meeting invite to your email.

regards,

Farabi

[Farabi]

Hello GB,

I have sent private email to ask your company email(currently you are using protonmail). Please reply so I can send meeting invitation to you.

regards,

Farabi

[UF1]

Farabi,

First, thanks for your consideration. I'm using a protonmail address as the mail of the company I'm working for doesn't log in Intel website. If you send me an email I can reply to, i can forward you my company's mail.

Beside that, please read the topic, i have described the issue we are facing several times: we only want to read the CRC generated by the cyclone10lp_crcblock.

I have instantiated the IP described in the chapter SEU mitigation, with signaltap I capture the IP signals but no output is generated.

Regards,

GB

2.15.0.0

[Farabi]

Hello,

Can you try this VHDL?

-----------

 i_cyclone10lp_crcblock : cyclone10lp_crcblock

   generic map (

   oscillator_divider => 1)

   port map (

   clk  => '0',

   shiftnld => '1',

   crcerror => s_altcrc_crcerror,

   regout => open);

-------------

regards,

Farabi

[UF1]

Farabi,

It doesn't work out.

The IP cyclone10lp_crcblock isn't instantiated in Quartus whereas it is under modelsim.

The IP cyclone10lp_crcblock doesn't appear in the IP catalog (Quartus 22.1).

I have tried to include the following library :

library cyclone10lp;
use cyclone10lp.cyclone10lp_components.all;

Any suggestion ?

Regards,

GB

2.15.0.0