Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs have moved to the Altera Community. Existing Intel Community members can sign in with their current credentials.
21618 Discussions

CycloneIII: LVDS_E_3R TX output voltage

Altera_Forum
Honored Contributor II
1,617 Views

Hi, 

 

I am currently using an EP3C10F256C8 Cyclone III in a project for LVDS transmission/mixing. It contains a 2x5-channel input on I/Obanks 5 + 6 

(true LVDS input: I/O standard LVDS) and a same-sized output on 

I/Obanks 3 + 4 (emulated LVDS output: I/O standard LVDS_E_3R). 

The used LVDS input/output frequencies range from 60 to 75 MHz, the 

whole system runs fine from a functional point of view. 

 

However, I am measuring a higher LVDS TX voltage on the LVDS_E_3R  

outputs, though following the Device Handbooks recommendations with a  

VCCIO = 2.5V and a 2x120 + 170 Ohms resistor network plus a differential  

load of 100 Ohms each. 

 

My measurements:  

VOS (dc offset) = 1.25 V, VOH = ca. 1.7 V, VOL = ca. 850mV. 

So I end up with a VOD (diff. amplitude) of ca. 850mV, higher than 

the ANSI standard allows. 

 

I have tried to change pre-emphasis and slow slew rate assignments, but  

with no luck/effect. A fix would be to re-calculate the 3R network. 

 

But I was wondering why the recommended settings end in these values 

or if I have overlooked anything related. 

 

Thanks for any hint, 

EP3Seb.
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
841 Views

A simple hand calculation of the voltage divider clarifies, that the differential voltage can't be 850 mV. I also don't remember to have seen a too large output with E_3R. So something must be expected wrong, either with your hardware setup or the measurement.

0 Kudos
Reply