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Honored Contributor I
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CycloneIV VCCD_PLL Decoupling

Hi, 

 

what is the appropriate ground connection for the VCCD_PLL pins? 

 

None of these have GND pins nearby in the E22 package, but the name suggests that this is a digital pin, so it is referenced to the digital GND. 

 

So far, I've connected these to VCCINT through a 1uH inductor and added a capacitor between VCCD_PLL and a via to the ground plane, but I wonder if this can be improved by connecting the capacitor to a specific GND pin. 

 

Simon
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Honored Contributor I
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Hi Simon - 

 

I recommend just following the guidelines provided by Altera for Cyclone IV: 

 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/dp/cyclone-iv/pcg-01008.p... 

 

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an592.pdf 

 

Unless specifically advised otherwise by an IC vendor (even then take it with a grain of salt) your best bet is always to drop a via to a solid ground plane vs routing a trace to a ground pin. And do not split the ground plane for Cyclone IV. 

 

Hope that helps. 

Bob
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Honored Contributor I
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I've set up the bypass caps for VCCINT and VCCIO like 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=13326  

 

in order to get these voltages as stable as possible. The same thing works for VCCA, but with VCCD_PLL I'm lost here: 

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=13327  

 

So far, it's attached to a via to the ground plane, but I think this could be done better. Neither the PCG nor the checklist give an indication what the return path for these pins is. 

 

Simon
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Honored Contributor I
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Simon - 

 

I recommend not using the approach of running traces to the IC pins from the bypass caps (your first image). Dropping vias from the caps directly to the power and ground planes is the best option. Inductance is the enemy here and the inductance is higher with the trace-to-pin approach. Read just about any book written in the last 25 years on high-speed digital design, signal integrity, etc, for an explanation. The only exception would be if you don't have solid power planes to connect to, but without solid planes you would have bigger problems to worry about than how to connect your bypass caps. 

 

Bob
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Honored Contributor I
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Yes, vias next to the caps are the next step here, because I still need to actually connect all these pins to the supply rails. 

 

For the connection between the caps and the pins, the only thing that could possibly have a lower inductance than a 2mm x 0.2mm trace would be a via to a cap on the bottom, but that is probably the same order of magnitude as the inductance of the bond wires inside the IC. 

 

Placing the caps on the bottom would indeed give a shorter path to whatever GND is the return path for the VCCD_PLL supply pin, but even then it would be good to know which one it is. I'd like to avoid parts on the bottom though.
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Honored Contributor I
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Agree with the suggestions by rsefton, in addition I would use smaller via sizes and probably 0402 bypass capacitors, but power supply traces rather 0.3 than 0.2 mm for lower inductance. 

 

The good point with your design is placing one bypass capacitor per supply pin.
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