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Altera_Forum
Honored Contributor I
895 Views

Unreliable D-FLOP

I've created a basic D-FLOP with a MAX3000 device. The FF clock input is driven by a debounced switch and the CPLD has an external reset chip and the FF reset input is mapped to the GCLR pin. When I push the button I should see a change of state on the FF output but sometimes it doesn't change. The CPLD is not clocked. I feel that I've missed something. My scope shows that the debounced input is good, supply rail is good, and GCLR is good. 

 

 

module Controller 

(switch,led,reset); 

 

//INPUT PINS:  

input switch; 

input reset; 

//OUTPUT PINS:  

output led; 

reg q1; 

//Define FLIP FLOP Logic Here 

always@(posedge switch or negedge reset) //SWITCH 1 D-flipflop 

if (~reset)  

begin 

q1 <= 1'b0; 

end  

else begin 

q1 <= ~q1; 

 

end  

initial q1 = 0; 

assign led = ~q1; //Output pin to LED driver 

endmodule
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3 Replies
Altera_Forum
Honored Contributor I
39 Views

It's a poor debounce circuit. RC time constant of 1 ms does not surely filter all bounce pulses. Bigger problem is that the capacitor is discharged without current limiting resistor, causes contact arcing and oscillations with possibly multiple edges in the 10 to 100 MHz range which can well trigger the FF twice.

Altera_Forum
Honored Contributor I
39 Views

FvM, 

 

I tacked a larger capacitor across the .1 and tried again. This time it worked perfectly. I'm puzzled because I've used this circuit successfully in the past, but my scope isn't capable of capturing the transients you talked about so I wouldn't have seen them. Thank you sir!
Altera_Forum
Honored Contributor I
39 Views

I would also add a 100 ohm or so series resistor to the switch, to avoid possible oscillations and increase switch lifetime.

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