CycloneV DDR3 Hard Controller: Many Failing Timing Paths

[JPB3RD]

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Hard controller implemented in Platform Designer (PD)

Rest of design passes timing

I've read through the EMI.pdf (External Memory Interface Handbook)

It looks like the PD generated sdc files are in the .qip, and this is included in the project settings files

All of the failing paths are internal to the logic included with the hard controller.

Memory clock: 400MHz (max), Device speed grade is 7 (this is fastest industrial temp)
Is this combination not possible? Is this listed somewhere?

Any suggestions on how to resolve this is appreciated. 

[yoichiK_intel]

Hi

Per EMIF spec estimator speed grad of 7 support 400Mhz of DDR3.   Which path is failing ?  Are launch and latch clock are same clock resource ?

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/external-memory-interfaces-support/emif.html

[JPB3RD]

Thank you for your reply. The issue has been resolved and I posted this. 

[JPB3RD]

This issue is resolved. Just to close this out in case it helps someone else, changing the input clock to the DDR3 controller from 200MHz to 100MHz caused all the timing paths to pass (!?). Strangest thing and I'm moving on :-).