CycloneV GX, four PLLs do not fit. Constraint?

[TJ-Takahashi]

Hello,
We are using PLL of CycloneV device.
Could you tell me about our followin question?

We use CycloneV GX 5CGXFC7D7F27C8N
We want to use four PLL's from a specific pin.
However, QUARTUS reported that only two FIT could be done.
Is this a constraint?

If it is a constraint, please tell me the corresponding document.

Referenced documents
cv_5v2.pdf , cv_52004.pdf , 5cgxfc7.xls

What we want to do
1st : CLK4p,CLK4n (Differential) to PLL1
2nd : CLK5p,CLK5n (Differential) to PLL2
3rd : CLK6p,CLK6n (Differential) to PLL3
4th : CLK7p,CLK7n (Differential) to PLL4

Pin layout:
K25(CLK4p) , K26(CLK4n)
N20(CLK5p) , M21(CLK5n)
R20(CLK6p) , P20(CLK6n)
T21(CLK7p) , T22(CLK7n)

Error screenshot is attached.

[SyafieqS]

Hi TJ,

Could you attach me the fit.rpt? This could be useful for investigation.

[SyafieqS]

May I know if there is any update from my previous request?

[TJ-Takahashi]

My response became very late.
I attached the fit.rpt.
Could you investigate this ?

This design is four LVDS.
These LVDS are the following.

bank 5B: (p)T21/(n)T22, (p)R20/(n)P20
bank 6A: (p)N20/(n)M21, (p)K25/(n)K26

[SyafieqS]

Tj,

Did you manage to work on this or still need help?

[SyafieqS]

Tj,

May need to see below KDB might be helping with the issue.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd12092015_970.html

[TJ-Takahashi]

Hello,

Thank you for your reply.
But this problem was not able to be solved.
So we gave up this PLL's using.
And we decided to reduce the number of PLL.

Thank you.