I am attempting to run a gate-level simulation on a design that uses the ALTLVDS macro. I am experiencing problems with the LVDS Transmitter while running the gate-level sim, I get the following warning:
** Warning: */cycloneiii_latch SETUP Low VIOLATION ON DATAIN WITH RESPECT TO ENA;# Expected := 0.503 ns; Observed := 0.276 ns; At : 5784.879 ns
the warning is generated from this area:
altlvds_tx_component|auto_generated|ddio_out|ddio_outa_9\/ddioreg_hi
As far as I am aware, there are no timing issues reported in TimeQuest, (I have constrained the input clock into this macro, set_clock_groups -asynchronous between it and the generated pll clock) as I was getting Recovery timing violations from the LVDS Reset to the internal LVDS nodes, the reset is synchronous to the input clock, the internal nodes are clocked by the pll clock.
The result here is X's propogating to the LVDS output in all but one of the back annotated timing operating conditions generated by Quartus.
Any ideas would be appreciated.
GLW
